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| copyright ? cirrus logic, inc. 2012 (all rights reserved) cirrus logic, inc. http://www.cirrus.com cs5484 four channel energy measurement ic features & description ? superior analog performance with ultra-low noise level and high snr ? energy measurement accuracy of 0.1% over 4000:1 dynamic range ? current rms measurement accuracy of 0.1% over 1000:1 dynamic range ? 4 independent 24-bit, 4 th -order, delta-sigma modulators for voltage and current measurements ? 4 configurable digital outputs for energy pulses, zero-crossing, or energy direction ? supports shunt resistor, ct, and rogowski coil current sensors ? on-chip measurements/calculations: - active, reactive, and apparent power - rms voltage and current - power factor and line frequency - instantaneous voltage, current, and power ? overcurrent, voltage sag, and voltage swell detection ? ultra-fast on-chip digital calibration ? internal register protection via checksum and write protection ? uart/spi? serial interface ? on-chip temperature sensor ? on-chip voltage reference (25ppm/c typ.) ? single 3.3v power supply ? ultra-fine phase compensation ? low power consumption: <13mw ? power supply configurations - gnda = gndd = 0v, vdda = +3.3v ? 5mmx5mm 28-pin qfn package ordering information see page 67 . description the cs5484 is a high-accuracy, four-channel, energy measurement analog front end. the cs5484 incorporates independent 4 th order delta-sigma analog-to-digital converters for every channel, reference circuitry, and the proven exl signal processing core to provide active, reactive, and apparent energy measurement. in addition, rms and power factor calculations are available. calculations are output through a configurable energy pulse, or direct uart/spi? serial access to on-chip registers. instantaneous current, voltage, and power measurements are also available over the serial port. multiple serial options are offered to allow customer flexibility. the spi provides higher speed, and the 2-wire uart mini mizes the cost of isolation where required. four configurable digital ou tputs provide energy pulses, zero-crossing, energy direction, and interrupt functions. interrupts can be generated for a variety of conditions including voltage sag or swell, overcurrent, and more. on-chip register integrity is assured via checksum and write protection. the cs5484 is designed to interface to a variety of voltage and current sensors including shunt resistors, current transformers, and rogowski coils. on-chip functionality makes digital calibration simple and ultra-fast, minimizing the time required at the end of the customer production line. perf ormance across temperature is ensured with an on-chip voltage reference with low drift. a single 3.3v power supply is required, and power consumption is low at <13mw. to minimize space requirements, the cs5484 is offered in a low-cost, 5mm x5mm 28-pin qfn package. vdda tx / sdo rx / sdi uart/spi serial interface configurable digital outputs reset calculation 4 th order ?? modulator hpf option do1 do2 hpf option vref+ vddd vref- system clock iin2+ iin2- pga iin1+ iin1- pga 10x cs5484 cs sclk ssel do3 vin1+ vin1- 10x vin2+ vin2- digital filter digital filter do4 mode hpf option digital filter hpf option digital filter m u x 4 th order ?? modulator 4 th order ?? modulator 4 th order ?? modulator gnda gndd voltage reference temperature sensor xin xout cpuclk clock generator jun?12 ds981f2
cs5484 2 ds981f2 table of contents 1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 2.1 analog pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.1 voltage inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.2 current inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.3 voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.1.4 crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2 digital pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.1 reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.2 cpu clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.3 digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 2.2.4 uart/spi? serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.5 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.6 uart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2.7 mode pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3. characteristics and specific ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 4. signal flow description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.1 analog-to-digital converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.2 decimation filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.3 iir filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 4.4 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.5 dc offset and gain correc tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.6 high-pass and phase matching filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.7 digital integrators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8 low-rate calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8.1 fixed number of sa mples averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.8.2 line-cycle synchronized averagi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.8.3 rms current and voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.4 active power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.8.5 reactive power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.6 apparent power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.7 peak voltage and current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.8.8 power factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.9 average active power offs et . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 4.10 average reactive po wer offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 zero-crossing detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 line frequency measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5 energy pulse generati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.5.1 pulse rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.5.2 pulse width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 voltage sag, voltage swe ll, and overcurrent detect ion . . . . . . . . . . . . . . . . . . . . .24 cs5484 ds981f2 3 5.7 phase sequence detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.8 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9 anti-creep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10 register protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10.1 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10.2 register checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. host commands and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 host commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1 memory access commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1.1 page select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1.2 register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.1.3 register write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.2 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1.3 checksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.1.4 serial time out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.2 hardware registers summ ary (page 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.3 software registers summary (page 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.4 software registers summary (page 17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.5 software registers summary (page 18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.6 register descript ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7. system calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1 calibration in general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1.1 offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1.1.1 dc offset calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1.1.2 ac offset calibrat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.1.2 gain calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.1.3 calibration order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.2 phase compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.3 temperature sensor calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 7.3.1 temperature offset and gain calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8. basic application circ uits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 9. package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 11. environmental, manufac turing, and handling informa tion . . . . . . . . . . . . . . . . . . . . . 67 12. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 cs5484 4 ds981f2 list of figures figure 1. oscillator connections............................................................................................... .... 7 figure 2. multi-device uart connections.................................................................................... 8 figure 3. uart serial frame format ........................................................................................... 8 figure 4. active energy load performance.................................................................................. 9 figure 5. reactive energy load performance............................................................................ 10 figure 6. irms load performance ............................................................................................. 10 figure 7. spi data and clock timing ......................................................................................... 15 figure 8. multi-device uart timing .......................................................................................... 15 figure 9. signal flow for v1, i1, p1, and q1 measurements ..................................................... 17 figure 10. signal flow for v2, i2, p2, and q2 measurements ................................................... 17 figure 11. low-rate calculations ............................................................................................... .18 figure 12. power-on reset timing ............................................................................................. 21 figure 13. zero-crossing level and zero-crossing output on dox ............................................ 22 figure 14. energy pulse generation and digital output control ................................................ 23 figure 15. sag, swell, and overcurrent detect .......................................................................... 24 figure 16. phase sequence a, b, c fo r rising edge transition ................................................ 25 figure 17. phase sequence c, b, a for rising edge transition ................................................ 26 figure 18. byte sequence for page select................................................................................. 27 figure 19. byte sequence for register read ............................................................................ 27 figure 20. byte sequence for register write ............................................................................. 27 figure 21. byte sequence for instructions.................................................................................. 27 figure 22. byte sequence for checksum ................................................................................... 28 figure 23. calibration data flow ............................................................................................... .62 figure 24. t register vs. force temp ........................................................................................ 64 figure 25. typical connection (single-phase, 3-wire, 12s electricity meter) ............................. 65 list of tables table 1. por thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 2. command format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 3. instruction format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 cs5484 ds981f2 5 1. overview the cs5484 is a cmos power measurem ent integrated circuit using four ?? analog-to-digital converters to measure two line voltages and two currents. op tionally, voltage2 channel can be used for temperature measurement. it calculates active, reactive, and appar ent power as well as rms voltage and current and peak voltage and current. it handles other system-related functions, such as energy pulse generation, voltage sag and swell, overcurrent and zero-crossing detection, and line frequency measurement. the cs5484 is optimized to interface to current tr ansformers, shunt resistors, or rogowski coils for current measurement and to resistive dividers or voltage transformers for voltage measurement. two full-scale ranges are provided on the current inputs to accommodate different types of current sensors. the cs5484?s four differential inputs have a common-mode input range from analog ground (gnda) to the positive analog supply (vdda). an on-chip voltage reference (typically 2.4 volts) is generated and provided at analog output, vref. four digital outputs (do1, do2, do3, and do4) prov ide a variety of output signals, and depending on the mode selected, provide energy pulses, zero-crossings, or other choices. the cs5484 includes a uart/spi? serial host interface to an external microcontroller. the serial select (ssel) pin is used to configure the serial port to be a spi or uart. spi signals include serial data input (sdi), serial data output (sdo), and serial clock (sclk). uart signals include serial data input (rx) and serial data output (tx). a chip select (cs ) signal allows multiple cs5484s to share the same serial interface with the microcontroller. cs5484 6 ds981f2 2. pin descriptions digital pins and serial data i/o digital outputs 15,16, 17,18 do1, do2, do3, do4 ? configurable digital outputs for energy pulses, interrupt, energy direction, and zero-crossings. reset 2 reset ? an active-low schmitt-trigger input used to reset the chip. serial data i/o 19,20 tx/sdo, rx/sdi ? uart/spi serial data output/input. serial clock input 21 sclk ? serial clock for the spi. chip select 22 cs ? chip select for the uart/spi. serial mode select 23 ssel ? selects the type of serial interface, uart or spi?. logic level one - uart selected. logic level zero - spi selected. operating mode select 24 mode ? connect to vdda for proper operation. analog inputs/outputs voltage inputs 7,8,6,5 vin1+, vin1-, vin2+, vin2- ? differential analog inputs for the voltage channels. current inputs 4,3,10,9 iin1+, iin1-, iin2+, iin2- ? differential analog inputs for the current channels. voltage reference input 12,11 vref+, vref- ? the internal voltage reference. a 0.1f bypass capacitor is required between these two pins. power supply connections internal digital supply 27 vddd ? decoupling pin for the internal 1.8v di gital supply. a 0.1f bypass capacitor is required between this pin and gndd. digital ground 26 gndd ? digital ground. positive analog supply 14 vdda ? the positive 3.3v analog supply. analog ground 13 gnda ? analog ground. clock generator crystal in crystal out 1,28 xin, xout ? connect to an external quartz crystal. alternatively, an ex ternal clock can be supplied to the xin pin to provi de the system clock for the device. cpu clock output 25 cpuclk ? output of on-chip oscillator which can drive one standard cmos load. thermal pad - no electrical connection. 9 8 7 6 5 4 3 2 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 top-down view 28-pin qfn package thermal pad xout vddd gndd cpuclk mode ssel cs vin1- iin2- iin2+ vref- vref+ gnda vdda xin reset iin1- iin1+ vin2- vin2+ vin1+ sclk rx/sdi tx/sdo do4 do3 do2 do1 do not connect cs5484 ds981f2 7 2.1 analog pins the cs5484 has two differential inputs (vin1 ??? vin2 ? ) for voltage input and two differential inputs ?? iin1 ?? iin2 ? ) for current1 and current2 inputs. the cs5484 also has two voltage reference pins (vref ? ) between which a bypass capacitor should be placed. 2.1.1 voltage inputs the output of the line voltage resistive divider or transformer is conn ected to the vin1 ? or vin2 ? input pins of the cs5484. the voltage channel is equipped with a 10x, fixed-gain amplifier. the full-scale signal level that can be applied to the voltage channel is 250mv. if the input signal is a sine wave, the maximum rms voltage is 250mvp/ ? 2 ? 176.78mv rms , which is approximately 70.7% of maximum peak voltage. 2.1.2 current inputs the output of the current-sensing shunt resistor, transformer, or rogowski coil is connected to the iin1 ? or iin2 ? input pins of the cs5484. to accommodate different current-sensing elements, the current channel incorporates a programmable gain amplifier (pga) with two selectable input gains, as described in the config0 register description (see section 6.6.1 configuration 0 (config0) ? page 0, address 0 on page 35.) there is a 10x gain setting and a 50x gain setting. the full-scale signal level for current channels is 50mv and 250mv for 50x and 10x gain settings, respectively. if the in put signal is a sine wave, the maximum rms voltage is 35.35mv rms or 176.78mv rms, which is approximately 70.7% of maximum peak voltage. 2.1.3 voltage reference the cs5484 generates a stable voltage reference of 2.4v between the vref ? pins. the reference system also requires a filter capacitor of at least 0.1f between the vref ? pins. the reference system is capable of providing a reference for the cs5484 but has limited ability to drive external circuitry. it is strongly recommended that nothing other than the required filter capacitor be connected to the vref ? pins. 2.1.4 crystal oscillator an external, 4.096mhz quartz crystal can be connected to the xin and xout pins, as shown in figure 1 . to re- duce system cost, each pin is supplied with an on-chip load capacitor. alternatively, an external clock source can be connected to the xin pin. 2.2 digital pins 2.2.1 reset input the active-low reset pin, when asserted for longer than 120s, will halt all cs 5484 operations and reset internal hardware registers and states. when de-asserted, an initializat ion sequence begins, setting default register values. to prevent erroneous noise-induced resets to the cs5484, an external pull-up resistor and a decoupling capacitor are necessary on the reset pin. 2.2.2 cpu clock output a logic-level clock output (cpuclk) is provided at the crystal frequency to drive another cs5484 ic or external microcontroller. writing ?1? to bit cpuclk_on of the config0 register enables the cpu clock output. after the cpu clock output is enabled, it can be disabled only by a power-on reset (por ) or by writing ?0? to the cpuclk_on bit. a hardware reset through pin/reset or a software reset instruction through the serial interface will not disable the cpu clock output. two phase choices are available on the cpuclk pin through bit icpuclk of the config0 register. different from the cpuclk_on bit, the icpuclk bit can be cleared by a por, a hardware reset, a software reset instruction, or a register write. 2.2.3 digital outputs the cs5484 provides four configurable digital outputs (do1-do4). they can be configured to output energy pulses, interrupt, zero-cross ings, or energy directions. refer to section 6.6.2 configuration 1 (config1) ? page 0, address 1 on page 36 for more details. xin xout c1 = 22pf c2 = 22pf figure 1. oscillator connections cs5484 8 ds981f2 2.2.4 uart/spi? serial interface the cs5484 provides five pins?ssel, rx/sdi, tx/sdo, cs , and sclk?for communication between a host microcontroller and the cs5484. ssel is an input that, when low, indicates to the cs5484 to use the spi port as the serial interface to communicate with the host microcontroller. the ssel pin has an internal weak pu ll-up. when the ssel pin is left unconnected or pulled high externally, the uart port is used as the serial interface. 2.2.5 spi the cs5484 provides a serial peripheral interface (spi) that operates as a slave device in 4-wire mode and supports multiple slaves on the spi bus. the 4-wire spi includes cs , sclk, sdi, and sdo signals. cs is the chip select input for the cs5484 spi port. a high logic level de-asserts it, tri-stating the sdo pin and clearing the spi interface. a low logic level enables the spi port. although the cs pin may be tied low for systems that do not require multiple sdo drivers, using the cs signal is strongly recommended to achieve more reliable spi communications. sclk is the serial clock input for the cs5484 spi port. serial data changes as a re sult of the falling edge of sclk and is valid at the rising edge. the sclk pin is a schmitt-trigger input. sdi is the serial data input to the cs5484. sdo is the serial data output from the cs5484. the cs5484 spi transmits and receives data msb first. refer to switching characteristics on page 14 and figure 7 on page 15 for more detailed information about spi timing. 2.2.6 uart the cs5484 device contains an asynchronous, full-duplex uart. the uart may be used in either standard 2-wire communication mode (rx/tx) for connecting a single device or 3-wire communication mode (rx/tx/ cs ) for connecting multiple devices. when connecting a single cs5484 device, cs should be held low to enable the uart. multiple cs5484 devices can communicate to the same master uart in the 3-wire mode by pulling a slave cs pin low during data transmissions. common rx and tx signals are provided to all the slave devices, and each slave device requires a separate cs signal for enabling communication to that slave. the multi-device uart mode connections are shown in figure 2 . figure 2. multi-device uart connections the multi-device uart mode timing diagram provides the timing requirements for the cs control (see figure 8. multi-device uart timing on page 15). the cs5484 uart operates in 8-bit mode, which transmits a total of 10 bits per byte. data is transmitted and received lsb first, with one start bit, eight data bits, and one stop bit. figure 3. uart se rial frame format the baud rate is defined in the serialctrl register. after chip reset, the default baud rate is 600, if mclk is 4.096mhz. the baud rate is based on the contents of bits br[15:0] in the serialctrl register and is calculated as follows: br[15:0] = baud rate x (524288/mclk) or baud rate = br[15:0] / (524288/mclk) the maximum baud rate is 512k if mclk is 4.096mhz. 2.2.7 mode pin the mode pin must be tied to vdda for normal operation. the mode pin is used primarily for factory test procedures. uart master slave 0 slave 1 slave n cs rx tx cs rx tx cs rx tx cs0 cs1 csn rx tx 0 1 2 7 idle stop 3 4 5 6 start data idle cs5484 ds981f2 9 3. characteristics and specifications recommended operating conditions power measuremen t characteristics notes: 1. specifications guaranteed by design and characterization. 2. active energy is tested with power factor (pf) = 1.0. reactive energy is tested with sin( ? ) = 1.0. energy error measured at system level using a single energy pul se. where: 1) one energy pulse = 0.5wh or 0.5varh; 2) vdda = +3.3v, t a = 25c, mclk = 4.096mhz; 3) system is calibrated. 3. calculated using register values; n 4000. 4. i rms error calculated using register values. 1) vdda = +3.3v; t a = 25c; mclk = 4.096mhz; 2) ac offset calibration applied. typical load performance ? energy error measured at system leve l using single energy pul se; where one energy pul se = 0.5wh or 0.5varh ?i rms error calculated using register values ? vdda = +3.3v; t a = 25c; mclk = 4.096mhz parameter symbol min typ max unit positive analog power supply vdda 3.0 3.3 3.6 v specified temperature range t a -40 - +85 c parameter symbol min typ max unit active energy all gain ranges (note 1 and 2) current channel input signal dynamic range 4000:1 p avg -0.1- % reactive energy all gain ranges (note 1 and 2) current channel input signal dynamic range 4000:1 q avg -0.1- % apparent power all gain ranges (note 1 and 3) current channel input signal dynamic range 1000:1 s-0.1-% current rms all gain ranges (note 1, 3, and 4) current channel input signal dynamic range 1000:1 i rms -0.1- % voltage rms (note 1 and 3) voltage channel input signal dynamic range 20:1 v rms -0.1- % power factor all gain ranges (note 1 and 3) current channel input signal dynamic range 1000:1 pf - 0.1 - % -1 -0.5 0 0.5 1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 percent error (%) current dynamic range (x : 1 ) lagging pf = 0.5 leading pf = 0.5 pf = 1 figure 4. active en ergy load performance cs5484 10 ds981f2 -1 -0.5 0 0.5 1 0 500 1000 1500 2000 2500 3000 3500 4000 4500 percent error (%) current dynamic range (x : 1 ) lagging sin( n ) = 0.5 leading sin( n ) = 0.5 sin( n ) = 1 figre 5. reaie energ load perorane -1 -0.5 0 0.5 1 0 500 1000 1500 percent error (%) current dynamic range (x : 1) irms error i rms error figre . i rms load perorane cs5484 ds981f2 11 analog characteristics ? min / max characteristics and specif ications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications ar e measured at nominal supply voltages and t a = 25c. ? vdda = +3.3v 10%; gnda = gndd = 0v. all voltages with respect to 0v. ? mclk = 4.096mhz. parameter symbol min typ max unit analog inputs (current channels) common mode rejection (dc, 50, 60hz) cmrr 80 - - db common mode+signal -0.25 - vdda v differential full-scale input range (gain = 10) [(iin+) ? (iin-)] (gain = 50) iin - - 250 50 - - mv p mv p total harmonic distortion (gain = 50) thd 90 100 - db signal-to-noise ratio (snr) (gain = 10) (gain = 50) snr - - 80 80 - - db db crosstalk from voltage inputs at full scale (50, 60hz) --115-db crosstalk from current input at full scale (50, 60hz) --115-db input capacitance ic - 27 - pf effective input impedance eii 30 - - k ? offset drift (without the high-pass filter) od - 4.0 - v/c noise (referred to input) (gain = 10) (gain = 50) n i - - 15 3.5 - - v rms v rms power supply rejection ratio (60hz) (note 7) (gain = 10) (gain = 50) psrr 60 68 65 75 - - db db analog inputs (voltage channels) common mode rejection (dc, 50, 60hz) cmrr 80 - - db common mode+signal -0.25 - vdda v differential full-scale input range [(vin+) ? (vin-)] vin - 250 - mv p total harmonic distortion thd 80 88 - db signal-to-noise ratio (snr) snr - 73 - db crosstalk from current inputs at full scale (50, 60hz) --115-db input capacitance ic - 2.0 - pf effective input impedance eii 2 - - m ? noise (referred to input) n v -40-v rms offset drift (without the high-pass filter) od - 16.0 - v/c power supply rejection ratio (60hz) (note 7) (gain = 10) psrr 60 65 - db temperature temperature accuracy (note 6) t-5-c cs5484 12 ds981f2 notes: 5. all outputs unloaded. all inputs cmos level. 6. temperature accuracy measured after calibration is performed. 7. measurement method for psrr: vdda = +3.3v, a 150mv (zero- to-peak) (60hz) sine wave is imposed onto the +3.3v dc supply voltage at the vdda pin. the ?+? and ?-? input pins of both input channels are shorted to gnda. the cs5484 is then commanded to continuous conversi on acquisition mode, and digital output data is collected for the channel under test. the (zero-to-peak) value of the digital sinusoi dal output signal is determined, and this va lue is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mv) that would need to be applied at the channel?s inputs in order to cause the same dig ital sinusoidal output. this vo ltage is then defined as v eq psrr is (in db) : voltage reference notes: 8. it is strongly recommended that no connection ot her than the required filter capacitor be made to vref. 9. the voltage at vref is measured across the temperature range. from these measurements the fo llowing formula is used to calculate the vref temperature coefficient: 10. specified at maximum recommended output of 1a sourcing. vref is a sensitive signal; the output of the vref circuit has a high output impedance so that the 0.1f reference capacitor pr ovides attenuation even to low-frequency noise, such as 50hz noise on the vref output. therefore vref intended for the cs5484 only and should not be connected to any external circuitry. the output impedance is sufficiently high that standard digital mult i-meters can significantly load this voltage. the accuracy of the metrology ic cannot be guaranteed when a multimeter or any component other than the 0.1f capacitor is attached to vref. if it is desired to measure vref for any reason other than a very c ourse indicator of vref functionality, cirrus recommends a very high input impedance multimeter such as the keithley model 2000 digital multimeter be used. cirrus cannot guarantee the accuracy of the metrology with this meter connected to vref. power supplies power supply currents (active state) i a+ (vdda = +3.3v) psca - 3.9 - ma power consumption (note 5) active state (vdda = +3.3v) stand-by state pc - - 12.9 4.5 - - mw mw parameter symbol min typ max unit reference (note 8) output voltage vref +2.3 +2.4 +2.5 v temperature coefficient (note 9) tc vref -25-ppm/c load regulation (note 10) ? v r -30-mv parameter symbol min typ max unit psrr 20 150 v eq ---------- - log ? = tc vref vref max vref min ? vref avg ------------------------------------------------------------ ?? ?? 1 t a max t a min ? --------------------------------------------- - ?? ?? 1.0 10 6 ? ?? = cs5484 ds981f2 13 digital characteristics ? min / max characteristics and specif ications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications ar e measured at nominal supply voltages and t a = 25c. ? vdda = +3.3v 10%; gnda = gndd = 0v. all voltages with respect to 0v. ? mclk = 4.096mhz. notes: 11. all measurements per formed under static conditions. 12. xout pin used for crystal on ly. typical drive current<1ma. parameter symbol min typ max unit master clock characteristics xin clock frequency internal gate oscillator mclk 2.5 4.096 5 mhz filter characteristics phase compensation range (60hz, owr = 4000hz) -10.79 - +10.79 input sampling rate - mclk/8 - hz digital filter output word rate (both channels) owr - mclk/1024 - hz high-pass filter corner frequency -3db -2.0-hz input/output characteristics high-level input voltage (all pins) v ih 0.6(vdda) - - v low-level input voltage (all pins) v il --0.6v high-level output voltage do1-do4, i out =+10ma (note 12) all other outputs, i out =+5ma v oh vdda-0.3 vdda-0.3 - - - - v v low-level output voltage do1-do4, i out =-12ma (note 12) all other outputs, i out =-5ma v ol - - - - 0.5 0.5 v v input leakage current i in -110a 3-state leakage current i oz --10a digital output pin capacitance c out -5-pf cs5484 14 ds981f2 switching characteristics ? min / max characteristics and specif ications are guaranteed over all recommended operating conditions . ? typical characteristics and specifications ar e measured at nominal supply voltages and t a = 25c. ? vdda = +3.3v 10%; gnda = gndd = 0v. all voltages with respect to 0v. ? logic levels: logic 0 = 0v, logic 1 = vdda. notes: 13. specified using 10% and 90% points on wa veform of interest. output loaded with 50pf. 14. oscillator start-up time varies with cr ystal parameters. this specification does not apply when using an external clock sour ce. 15. the maximum sclk is 2mhz during a byte transaction. t he minimum 1s idle time is required on the sclk between two consecutive bytes. parameter symbol min typ max unit rise times do1-do4 (note 13) any digital output except do1-do4 t rise - - - 50 1.0 - s ns fall times do1-do4 (note 13) any digital output except do1-do4 t fall - - - 50 1.0 - s ns start-up oscillator st art-up time xtal = 4.096 mhz (note 14) t ost -60-ms spi timing serial clock frequency (note 15) sclk - - 2 mhz serial clock pulse width high pulse width low t 1 t 2 200 200 - - - - ns ns cs enable to sclk falling t 3 50 - - ns data set-up time prior to sclk rising t 4 50 - - ns data hold time after sclk rising t 5 100 - - ns sclk rising prior to cs disable t 6 1- -s sclk falling to new data bit t 7 --150ns cs rising to sdo hi-z t 8 --250ns uart timing cs enable to rx start bit t 9 5- -ns stop bit to cs disable t 10 1- -s cs disable to tx idle hold time t 11 --250ns cs5484 ds981f2 15 sdo sdi t 1 t 2 t 3 t 4 t 5 t 6 t 7 t 8 cs sclk msb msb msb-1 msb-1 intermediate bits intermediate bits lsb lsb figure 7. spi data and clock timing tx rx t 9 t 11 cs start lsb lsb data msb stop start data msb stop stop idle optional overlap instruction * idle t 10 idle * reading registers during the optional overlap instruction requires the start to occur during the last byte transmitted by the part figure 8. multi-device uart timing cs5484 16 ds981f2 absolute maximum ratings notes: 16. vdda and gnda must satisfy [(vdda) ? (gnda)] ? + 4.0v. 17. applies to all pins, includi ng continuous overvoltage conditions at the analog input pins. 18. transient current of up to 100 ma will not cause scr latch-up. 19. applies to all pins, except vref . 20. total power dissipation, including all input currents and output currents. 21. applies to all pins. warning: operation at or beyond these limits may re sult in permanent damage to the device. normal operation is not guaranteed at these extremes. parameter symbol min typ max unit dc power supplies (note 16) vdda -0.3 - +4.0 v input current (notes 17 and 18) i in -- 10ma input current for power supplies - - - 50 - output current (note 19) i out -- 100ma power dissipation (note 20) p d -- 500mw input voltage (note 21) v in - 0.3 - (vdda) + 0.3 v junction-to-ambient thermal impedance 2 layer board 4 layer board ? ja - - 53 43 - - c/w c/w ambient operating temperature t a -40 - 85 c storage temperature t stg -65 - 150 c cs5484 ds981f2 17 4. signal flow description the signal flow for voltage measurement, current measurement, and the other calculations is shown in figures 9 , 10 , and 11 . the signal flow consists of two current channels and two voltage channels. the current and voltage channels have differential input pins. 4.1 analog-to-digital converters all four input channels use fourth-order delta-sigma modulators to convert the analog inputs to single-bit digital data streams. the converters sample at a rate of mclk/8. this high sampling provides a wide dynamic range and simplifies anti- alias filter design. 4.2 decimation filters the single-bit modulator output data is widened to 24 bits and down sampled to mclk/1024 with low-pass decimation filters. these decimation filters are third-order sinc filters. the filter outputs pass through an iir "anti-sinc" filter. 4.3 iir filters the iir filters are used to compensate for the amplitude roll-off of the decimation filters. the droop-correction filter flattens the magnitude response of the channel out to the nyquist frequency, thus allowing for accurate measurements of up to 2 khz (mclk = 4.096 mhz). by default, the iir filters are enabled. the iir filters can be bypassed by setting the iir_off bit in the config2 register. 4.4 phase compensation phase compensation changes the phase of voltage relative to current by adding a delay in the decimation filters. the amount of phase shift is set by the pc register bits cpccx[1:0] and fpccx[8:0] for current channels. bits cpccx[1:0] set the delay for the voltage channels. mux vin1 sinc 3 + x iin1 sinc 3 + x pga + + ? hpf 4 th order ? modulator 4 th order ? modulator x10 x delay ctrl x x x 2 ? mux x pmf hpf pmf iir iir phase shift config 2 x epsilon delay ctrl int ? registers q1 v1 p1 i1 sys gain ... ... i1flt[1:0] v1flt[1:0] v1 dcoff i1 dcoff i1 gain v1 gain pc ... ... fpcc1[8:0] cpcc1[1:0] ... figure 9. signal flow for v1, i1, p1, and q1 measurements mux vin2 sinc 3 + x iin2 sinc 3 + x pga + + ? hpf 4 th order ? modulator 4 th order ? modulator x10 x delay ctrl x x x 2 ? mux x pmf hpf pmf iir iir phase shift x epsilon delay ctrl int ? registers q2 v2 p2 i2 sys gain v2 dcoff i2 dcoff i2 gain v2 gain pc config 2 ... ... i2flt[1:0] v2flt[1:0] ... ... fpcc2[8:0] cpcc2[1:0] ... figure 10. signal flow for v2, i2, p2, and q2 measurements cs5484 18 ds981f2 fine phase compensation control bits, fpccx[8:0], provide up to 1/owr delay in the current channel. coarse phase compensation control bits, cpccx[1:0], provide an additional 1 /owr delay in the current channels or up to 2/owr delay in the voltage channel. negative delay in the voltage channel can be implemented by setting longer delay in the current channel than the voltage channel. for a owr of 4000hz, the delay range is 500s, a phase shift of 8.99 at 50hz and 10.79 at 60 hz. the step size is 0.008789 at 50 hz and 0.010547 at 60hz. 4.5 dc offset and gain correction the system and cs5484 in herently have component tolerances, gain, and offset errors, which can be removed using the gain and offset registers. each measurement channel has its own set of gain and offset registers. for every instantaneous voltage and current sample, the offset and gain values are used to correct dc offset and gain errors in the channel (see section 7. system calibration on page 62 for more details). 4.6 high-pass and ph ase matching filters optional high-pass filters (hpf in figures 9 and 10 ) remove any dc component from the selected signal paths. each power calculat ion contains a current and voltage channel. if an hpf is enabled in only one channel, a phase-matching filter (pmf) should be applied to the other channel to match the phase response of the hpf. for ac power measurement, high-pass filters should be enabled on the voltage and current channels. for information about how to enable and disable the hpf or pmf on each channel, refer to section 6.6.3 configuration 2 (config2) ? page 16, address 0 on page 38. 4.7 digital integrators optional digital integrators (int in figures 9 and 10 ) are implemented on both current channels (i1, i2) to compensate for the 90o phase shift and 20db/decade gain generated by the rogowski coil current sensor. when a rogowski coil is used as the current sensor, the integrator (int) should be enabled on that current channel. for information about how to enable and disable the int on each current channel, refer to section 6.6.3 configuration 2 (config2) ? page 16, address 0 on page 38. 4.8 low-rate calculations all the rms and power result s come from low-rate cal- culations by averaging the output word rate (owr) in- stantaneous values over n samples, where n is the value stored in the samplecount register. the low-rate interval or averaging period is n divided by owr (4000hz if mclk = 4.096mhz). the cs5484 provides two averaging modes for low-rate calculations: fixed number of samples averaging mode and line-cycle synchronized averaging mode. by default, the cs5484 averages with the fixed num- ber of samples averaging mode. by setting the avg_mode bit in the config2 register, the cs5484 will use the line-cycle synchronized averaging mode. 4.8.1 fixed number of samples averaging n is the preset value in the samplecount register and should not be set less th an 100. by default, the samplecount is 4000. with mclk = 4.096mhz, the averaging period is fixed at n/4000 = 1 second, regardless of the line frequency. ? n n ? n n ? n n ? ? n n ? ? registers mux ... ... apcm config 2 v1(v2) i1 (i2) p1 (p2) q1 (q2) i1 acoff (i2 acoff ) s1 (s2) ? ? pf1 (pf2) x i1 rms (i2 rms ) v1 rms (v2 rms ) q1 avg (q2 avg ) p1 avg (p2 avg ) - + q1 off (q2 off ) ? + + p1 off (p2 off ) ? + + x x + + inverse figure 11. low-rate calculations cs5484 ds981f2 19 4.8.2 line-cycle synchronized averaging when operating in line-cycle synchronized averaging mode, and when line frequency measurement is enabled (see section 5.4 line frequency measurement on page 22), the cs5484 uses the voltage (v) channel zero crossings and measured line frequency to automatically adjust n such that the averaging period will be equal to the number of half line-cycles in the cyclecount register. for example, if the line frequency is 51hz, and the cyclecount register is set to 100, n will be 4000 ? (100/2)/51 = 3921 during continuous conversion. n is self-adjusted according to the line frequency, therefore the averaging period is always close to the whole number of half line-cycles, and the low-rate calculation result s will minimize ripple and maximize resolution, especi ally when the line frequency varies. before starting a low-rate conversion in the line-cycle synchronized averaging mode, the samplecount register should not be changed from its default value of 4000, and bit afc of the config2 register must be set. during continuous conversion, the host processor should not change the samplecount register. 4.8.3 rms current and voltage the root mean square ( rms in figure 11 ) calculations are performed on n instantaneous current and voltage samples using equation 1: 4.8.4 active power the instantaneous voltage and current samples are multiplied to obtain the instantaneous power ( p1, p2 ) (see figures 9 and 10 ). the product is then averaged over n samples to compute active power ( p1avg, p2avg ). 4.8.5 reactive power instantaneous reactive power ( q1, q2 ) are sample rate results obtained by multip lying instantaneous current ( i1, i2 ) by instantaneous quadrature voltage ( v1q, v2q ), which are created by phase shifting instantaneous voltage ( v1, v2 ) 90 degrees using first-order integrators (see figures 9 and 10 ). the gain of these integrators is inversely related to line frequency, so their gain is corrected by the epsilon register, which is based on line frequency. reactive power ( q1 avg , q2 avg ) is generated by integrating the instantaneous quadrature power over n samples. 4.8.6 apparent power by default, the cs5484 calculates the apparent power ( s1 , s2 ) as the product of rms voltage and current, as shown in equation 2: the cs5484 also provides an alternate apparent power calculation method. the alternate apparent power method uses real power ( p1 avg , p2 avg ) and reactive power ( q1 avg , q2 avg ) to calculate apparent power. see equation 3: the apcm bit in the config2 register controls which method is used for apparent power calculation. 4.8.7 peak voltage and current peak current ( i1 peak , i2 peak ) and peak voltage ( v1 peak , v2 peak ) are calculated over n samples and recorded in the corresponding channel peak register documented in the register ma p. this peak value is up- dated every n samples. 4.8.8 power factor power factor ( pf1 , pf2 ) is active power divided by ap- parent power. the sign of the power factor is deter- mined by the active power. see equation 4: rms i n 2 n0 = n1 ? ? n ------------------- - = v rms v n 2 n0 = n1 ? ? n ---------------------- = [eq: 1] sv rms i rms ? = [eq: 2] sq avg 2 p avg 2 + = [eq: 3] pf p active s ---------------------- = [eq: 4] cs5484 20 ds981f2 4.9 average active power offset the average active powe r offset registers, p1 off ( p2 off ), can be used to offset erroneous power sources resident in the system not originating from the power line. residual power offs ets are usually caused by crosstalk into current channels from voltage channels, or from ripple on the meter?s or chip?s power supply, or from inductance from a nearby transformer. these offsets can be either positive or negative, indicating crosstalk coupling either in phase or out of phase with the applied voltage input. the power offset registers can compensate for either condition. to use this feature, measure the average power at no load. take the measured result (from the p1 avg ( p2 avg ) register), invert (negate) the value, and write it to the associated average active power offset register, p1 off ( p2 off ). 4.10 average react ive power offset the average reactive po wer offset registers, q1 off ( q2 off ), can be used to offset erroneous power sources resident in the system not originating from the power line. residual reactive power offsets are usually caused by crosstalk into current channels from voltage channels, or from ripple on the meter?s or chip?s power supply, or from inductance from a nearby transformer. these offsets can be either positive or negative, depending on the phase angle between the crosstalk coupling and the applied voltage. the reactive power offset registers can compensat e for either condition. to use this feature, measure the average reactive power at no load. take the measured result from the q1 avg ( q2 avg ) register, invert (negate) the value and write it to the associated reactive power offset register, q1 off ( q2 off ). cs5484 ds981f2 21 5. functional description 5.1 power-on reset the cs5484 has an internal power supply supervisor circuit that monitors the vdda and vddd power supplies and provides the master reset to the chip. if any of these voltages are in the reset range, the master reset is triggered. the cs5484 has dedicated power-on reset (por) circuits for the analog supply and digital supply. during power-up, both supplies have to be above the rising threshold for the master reset to be de-asserted. each por is divided into two blocks: rough and fine. rough por triggers the fine por. rough por depends only on the supply voltage. the trip point for the fine por is dependent on bandgap voltage for precise control. the por circuit also acts as a brownout detect. the fine por detects supply drops and asserts the master reset. the rough and fine pors have hysteresis in their rise and fall thresholds, which prevents the reset signal from chattering. figure 12 shows the por outputs for each of the power supplies. the por_fine_vdda and por_fine_vddd signals are and-ed to form the actual power-on reset signal to the digital circuity. the digital circuitry, in turn, holds the master reset signal for 130ms and then de-asserts the master reset. table 1. por thresholds 5.2 power saving modes power saving modes for the cs5484 are accessed through the host commands (see section 6.1 host commands on page 27). ? standby: powers down all the adcs, rough buffer, and the temperature sensor. standby mode disables the system time calculations. use the wake-up command to come out of standby mode. ? wake-up: clears the adc power-down bits and starts the system time calculations. after any of these commands are completed, the drdy bit is set in the status0 register. 5.3 zero-crossing detection zero-crossing detection logic is implemented in the cs5484. one current and one voltage channel can be selected for zero-crossing detection. the izx_ch and vzx_ch control bits in the config0 register are used to select the zero-crossing cha nnel. a low-pass filter can be enabled by setting the zx_lpf bit in register config2 . the low-pass filter has a cut-off frequency of 80hz. it is used to eliminate any harmonics and help the zero-crossing detection on the 50hz or 60hz fundamental component. the zero-crossing level registers are used to set the minimum threshold over which the channel peak must exceed in order for the zero-crossing detection logic to function. there are two separate zero-crossing level registers: vzx level is the threshold for the voltage channels, and izx level is the threshold for the current channels. vdda por_rough_vdda por_fine_vdda vddd por_rough_vddd por_fine_vddd por_fine_vdda por_fine_vddd master reset 130 ms v th1 v th2 v th5 v th6 v th3 v th4 v th7 v th8 figure 12. power-on reset timing typical por threshold rising falling vdda rough v th1 =2.34v v th6 =2.06v fine v th2 =2.77v v th5 =2.59v vddd rough v th3 =1.20v v th8 =1.06v fine v th4 =1.51v v th7 =1.42v cs5484 22 ds981f2 5.4 line frequency measurement if the automatic frequency calculation (afc) bit in the config2 register is set, the line frequency measurement on the voltage channel w ill be enabled. the line frequency measurement is based on a number of voltage channel zero crossings. this number is 100 by default and configurable through the zx num register (see section 6.6.76 on page 61). the epsilon register will be updated automatica lly with the line frequency information. the frequency update (fup) bit in the status0 interrupt status register is set when the frequency calculation is completed. when the line frequency is 50hz and the zx num register is 100, the epsilon register is updated every one second with a resolution of less than 0.1%. a larger zero-crossing number in the zx num register will increase line frequency measurement resolution and the period. note that the cs5484 line frequency measurement function does not support the line frequency out of the range of 40hz to 75hz. the epsilon register is also used to set the gain of the 90 phase shift filter used in the quadrature power calculation. the value in the epsilon register is the ratio of the line frequency to the output word rate (owr). for 50hz line frequency and 4000hz owr, epsilon is 50/4000 (0.0125) (the default). for 60hz line frequency, it is 60/4000 (0.015). 5.5 energy pulse generation the cs5484 provides four independent energy pulse generation blocks (epg1, epg2, epg3, and epg4) in order to simultaneously output active, reactive, and apparent energy pulses on any of the four digital output pins (do1, do2, do3, and do4). the energy pulse frequency is proportional to the magnitude of the power. the energy pulse output is commonly used as the test output of a power meter. the host microcontroller can also use the energy pulses to easily accumulate the energy. refer to figure 14 . v zx level izx level if |v peak | > vzx level , then voltage zero-crossing detection is enabled. if |i peak | > izx level , then current zero-crossing detection is enabled. zero-crossing output on dox pin pulse width = 250s v( t ), i( t ) dox t t if |v peak | ? vzx level , then voltage zero-crossing detection is disable d. if |i peak | ? izx level , then current zero-crossing detection is disabled. figure 13. zero-crossing level and zero-crossing output on dox cs5484 ds981f2 23 after reset, all four energy pulse generation blocks are disabled (doxmode[3:0] = hi- z). to output a desired energy pulse to a dox pin, it is necessary to follow the steps below: 1. write to register pulsewidth (page 0, address 8) to select the energy pulse width and pulse frequency range. 2. write to register pulserate (page 18, address 28) to select the energy pulse rate. 3. write to register pulsectrl (page 0, address 9) to select the input to each energy pulse generation block. 4. write ?1? to bit epgx_on of register config1 (page 0, address 1) to enable the desired energy pulse generation blocks. 5. wait at least 0.1 seconds. 6. write bits doxmode[3:0] of register config1 to select dox to output pulses from the appropriate energy pulse generation block. 7. send dsp instruction (0xd5) to begin continuous conversion. p sum sign q sum sign p1 sign p2 sign q1 sign q2 sign v1/v2 crossing i1/i2 crossing do1_od ( config1 ) do2_od ( config1 ) do4_od ( config1 ) ( pulsectrl ) epgxin[3:0] doxmode[3:0] ( config1 ) do4 do2 do1 hi-z interrupt p sum q sum s sum p1 avg p2 avg q1 avg q2 avg s1 avg s2 avg pulse rate epgx_on ( config1 ) mclk ( pulsewidth ) pw[7:0] ( pulsewidth ) freq_rng[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 energy pulse generation (epg1) energy pulse generation (epg2) energy pulse generation (epg3) 4 4 8 4 digital output mux (do3) digital output mux (do2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 digital output mux (do1) reserved reserved energy pulse generation (epg4) do3_od ( config1 ) do3 digital output mux (do4) figure 14. energy pu lse generation and digital output control cs5484 24 ds981f2 5.5.1 pulse rate before configuring the pulserate register, the full-scale pulse rate needs to be calculated and the frequency range needs to be specified through freq_rng[3:0] bits in the pulsewidth register. refer to section 6.6.6 pulse output width (pulsewidth) ? page 0, address 8 on page 41. the freq_rng[3:0] bits should be set to b[0110]. for example, if a meter has the meter constant of 1000imp/kwh, a maximum voltage (u max ) of 240 v, and a maximum current (i max ) of 100a, the maximum pulse rate is: [1000x(240x100/1000)]/3600 = 6.6667hz. assume the meter is calibrated with u max and i max , and the scale register contains the default value of 0.6. after gain calibra tion, the power register value will be 0.36, which represents 240x100 = 24kw or 6.6667hz pulse output rate. the fu ll-scale pulse rate is: f out = 6.6667/0.36 = 18.5185hz. the cs5484 pulse generation block behaves as follows: ? the pulse rate generated by full-scale (1.0decimal) power register is: f out =( pulserate x2000)/2 freq_rng ?the pulserate register value is: pulserate = (f out x2 freq_rng )/2000 = (18.5186x64)/2000 = 0.5925952 = 0x4bda29 5.5.2 pulse width the pulsewidth register defines the active-low time of each energy pulse: active-low = 250s+( pulsewidth /64000). by default, the pulsewidth register value is 1, and the active-low time of each en ergy pulse is 265.6s. note that the pulse width should never exceed the pulse period. 5.6 voltage sag, voltage swell, and overcurrent detection voltage sag detection is used to determine when the voltage falls below a predetermined level for a specified interval of time (duration). voltage swell and overcurrent detection determine when the voltage or current rises above a predetermined level for the duration. the duration is set by the value in the v1sag dur ( v2sag dur ), v1swell dur ( v2swell dur ), and i1over dur ( i2over dur ) registers. setting any of these to zero (default) disables th e detect feature for the given channel. the value is in output word rate (owr) samples. the predetermined level is set by the values in the v1sag level ( v2sag level ), v1swell dur ( v2swell dur ), and i1over level ( i2over level ) registers. for each enabled input channel, the measured value is rectified and compared to the associated level register . over the duration window, the number of samples above and below the level are counted. if the number of samples below the level exceeds the number of samples above, a status0 register bit v1sag (v2sag) is set, indicating a sag condition. if the number of samples above the level exceeds the number of samples below, a status0 register bit v1swell (v2swell) or i1over (i2over) is set, indicating a swell or overcurrent condition (see figure 15 ). level duration figure 15. sag, swell, and overcurrent detect cs5484 ds981f2 25 5.7 phase sequence detection polyphase meters using multiple cs5484 devices may be configured to sense the succession of voltage zero-crossings and determine which phase order is in service. the phase sequence detection within cs5484 involves counting the number of owr samples from a starting point to the next voltage zero-crossing rising edge or falling for each pha se. by comparing the count for each phase, the phase sequence can be easily determined: the smallest coun t is first, and the largest count is last. the phase sequence detection and control ( psdc ) register provides the coun t control, zero-crossing direction and count results. writing '0' to bit done and '10110' to bits code[4:0] of the psdc register followed by a falling edge on the rx pin will initiate the phase sequence detection circuit. the rx pin must be held low for a minimum of 500ns. when the device is in uart mode, it is recommended that a 0xff command be written to all parts to start the phase sequence detection. this command is ignored by the uart interface and a checksum is not needed. multiple cs5484 devices in a polyphase meter must receive the register writing and the rx falling edge at the same time so that all cs5484 devices start to count simultaneously. bit dir of the psdc register specifies the direction of the next zero-crossing at which the count stops. if bit dir is '0', the count stops at the next negative-to-positive zero crossi ng. if bit dir is '1', the count stops at the next positive-to-negative zero-crossing. when the count stops, the done bit will be set by the cs5484, and then the count result of each phase may be read from bits pscnt[6:0] of the psdc register. if the pscnt[6:0] bits are equal to 0x00, 0x7f or greater than 0x64 (for 50hz) or 0x50 (for 60hz), then a measurement error has occurred, and the measurement results should be disregarded. this could happen when the voltage input signal amplitude is lower than the amplitude specified in the vzx level register. to determine the phase order, the pscnt[6:0] bit count from each cs5484 is sorted in ascending order. figure 16 and figure 17 illustrate how phase sequence detection is performed. phase sequences a, b, and c for the default rising edge transition are illustrated in figure 16 . the pscnt[6:0] bits from the cs 5484 on phase a will have the lowest count, followed by the pscnt[6:0] bits from the cs5484 on phase b with the middle count, and the pscnt[6:0] bits from the cs5484 on phase c with the highest count. phase sequences c, b, and a for rising edge transition are illustrated in figure 17 . the pscnt[6:0] bits from the cs5484 on phase c will have the lowest count, followed by the pscnt[6:0] bits from the cs5484 on phase b with the middle count, and the pscnt[6:0] bits from the cs5484 on phase a with the highest count. 5.8 temperature measurement the cs5484 has an internal temperature sensor, which is designed to measure temperature and optionally compensate for temperature drift of the voltage reference. temperature measurements are stored in the temperature register ( t ), which, by default, is configured to a range of 128 degrees on the celsius (c) scale. the application program can change both the scale and range of temperature by changing the temperature gain ( t gain ) and temperature offset ( t off ) registers. figure 16. phase sequence a, b, c for rising edge transition -2 0 2 phase a channel -2 0 2 phase b channel -2 0 2 phase c channel write 0x16 to psdc register start on the falling edge on the rx pin stop stop stop phase c count phase b count phase a count a b c cs5484 26 ds981f2 the temperature sensor and v2 input share the same delta-sigma modulator on the second voltage channel. by default, the temperature measurement is disabled, and the delta-sigma modulator is used for v2 measurement. to enable temperature measurement, set config0 register bit 23, bit 22, and bit 13. the temperature register ( t ) updates every 2240 output word rate (owr) samples. the status0 register bit tup indicates when t is updated. the temperature measurement and the second voltage channel, v2, share the same delta-sigma modulator, so the v2 measurement will be usin g the v1 delta-sigma modulator output when temperature measurement is enabled. 5.9 anti-creep the anti-creep (no-load threshold) is used to determine if a no-load condition is detected. the | p sum | and | q sum | are compared to the value in the no-load threshold register ( load min ). if both | p sum | and | q sum | are less than this threshold, then p sum and q sum are forced to zero. if s sum is less than the value in load min register, then s sum is forced to zero. 5.10 register protection to prevent the critical configuration and calibration registers from unintended changes, the cs5484 provides two enhanced register protection mechanisms: write protection and automatic checksum calculation. 5.10.1 write protection setting the dsp_lck[4:0] bits in the reglock register to 0x16 enables the cs5484 dsp lockable registers to be write-protected from the calculation engine. setting the dsp_lck[4:0] bits to 0x09 disables the write-protection mode. setting the host_lck[4:0] bits in the reglock register to 0x16 enables the cs5484 host lockable registers to be write-protected from the serial interface. setting the host_lck[4:0] bits to 0x09 disables the write-protection mode. for registers that are dsp lockable, host lockable, or both, refer to sections 6.2 hardware registers summary (page 0) on page 29, 6.3 software registers summary (page 16) on page 31, and 6.4 software registers summary (page 17) on page 33. 5.10.2 register checksum all the configuration and calibration registers are protected by checksum, if enabled. refer to 6.2 hardware registers summary (page 0) on page 29, 6.3 software registers summary (page 16) on page 31, and 6.4 software registers summary (page 17) on page 33. the checksum for all registers marked with an asterisk symbol (*) is calculated once every low-rate cycle. the checksum resu lt is stored in the regchk register. after the cs5484 has been fully configured and loaded with the calibrations, the host microcontroller should keep a copy of the checksum ( regchk_copy ) in its memory. in normal operation, the host microcontroller can read the regchk register and compare it with the saved copy of the regchk register. if the two values mismatch, a reload of configurations and calibrations into the cs5484 is necessary. the automatic checksum computation can be disabled by setting the reg_csum_off bit in the config2 register. -2 0 2 phase a channel -2 0 2 phase b channel -2 0 2 phase c channel stop stop stop phase c count phase b count phase a count a b c write 0x16 to psdc register start on the falling edge on the rx pin figure 17. phase sequence c, b, a for rising edge transition cs5484 ds981f2 27 6. host commands and registers 6.1 host commands the first byte sent to the cs5484 sdi/rx pin contains the host command. four ty pes of host commands are required to read and write registers and instruct the calculation engine. the two most significant bits (msbs) of the host command defines the function to be performed. the following table depicts the types of commands. table 2. command format 6.1.1 memory access commands the cs5484 memory has 12-bit addresses and is organized as p 5 p 4 p 3 p 2 p 1 p 0 a 5 a 4 a 3 a 2 a 1 a 0 in 64 pages of 64 addresses each. the higher 6 bits specify the page number. the lower 6 bits specify the address within the selected page. 6.1.1.1 page select a page select command is designated by setting the two msbs of the command to binary ?10?. the page select command provides the cs5484 with the page number of the register to access . register read and write commands access 1 of 64 registers within a specified page. subsequent register reads and writes can be performed once the page has been selected. figure 18. byte sequence for page select 6.1.1.2 register read a register read is designated by setting the two msbs of the command to binary ?00?. the lower 6 bits of the register read command are the lower 6 bits of the 12-bit register address. after the register read command has been received, the cs5484 will send 3 bytes of register data onto the sdo/tx pin. figure 19. byte sequence for register read 6.1.1.3 register write a register write command is designated by setting the two msbs of the command to binary ?01?. the lower 6 bits of the register write command are the lower 6 bits of the 12-bit register addres s. a register write command must be followed by 3 bytes of data. figure 20. byte sequence for register write 6.1.2 instructions an instruction command is designated by setting the two msbs of the command to binary '11'. an instruction command will interrupt any pr ocess currently running and initiate a new process in the cs5484. figure 21. byte sequence for instructions these new processes include calibration, power control, and soft reset. the following table depicts the types of instructions. these new processes include calibration, power control, and soft reset. the following table depicts the types of instructions. note that when the cs5484 is in continuous conversion mode, an unexpected or invalid instruction command could cause the device to stop continuo us conversion and enter an unexpected operation mode. the host processor should keep monitoring the cs5484 operation status and react accordingly. function binary value note register read 0 0 a 5 a 4 a 3 a 2 a 1 a 0 a [5:0] specifies the register address. register write 0 1 a 5 a 4 a 3 a 2 a 1 a 0 page select 1 0 p 5 p 4 p 3 p 2 p 1 p 0 p [5:0] specifies the page. instruction 1 1 c 5 c 4 c 3 c 2 c 1 c 0 c [5:0] specifies the instruction. sd i/rx page select cmd . sdo/tx sdi/rx data data data read cmd . sd i/rx data data data write cmd. sd i/rx instruction cs5484 28 ds981f2 table 3. instruction format 6.1.3 checksum to improve the communicati on reliability on the serial interface, the cs5484 provides a checksum mechanism on transmitted and received signals. checksum is disabled by default but can be enabled by setting the appropriate bit in the serialctrl register. when enabled, both host and cs5484 are expected to send one additional checksum byte after the normal command byte and applicable 3-byte register data has been transmitted. the checksum is calculated by subtracting each transmit byte from 0xff. any overflow is truncated and the result wraps. the cs 5484 executes the command only if the checksum transmitted by the host matches the checksum calculated loca lly. otherwise, it sets a status bit (rx_csum_err in the status0 register), ignores the command, and clears the serial interface in preparation for the next transmission. figure 22. byte sequence for checksum 6.1.4 serial time out in case a transaction from th e host is not completed (for example, a data byte is missing in a register write), a time out circuit will reset the interface after 128ms. this will require that each byte be sent from the host within 128ms of the previous byte. function binary value note controls 0 c 4 c 3 c 2 c 1 c 0 0 00001 - software reset 0 00010 - standby 0 00011 - wakeup 0 10100 - single conv. 0 10101 - continuous conv. 0 11000 - halt conv. c [5] specifies the instruction type: 0 = controls 1 = calibrations calibrations 1 c 4 c 3 c 2 c 1 c 0 1 00 c 2 c 1 c 0 dc offset 1 10 c 2 c 1 c 0 ac offset* 1 11 c 2 c 1 c 0 gain for calibrations, c [4:3] specifies the type of calibration. *ac offset calibra- tion valid only for cur- rent channel 1c 4 c 3 c 2 c 1 c 0 1 c 4 c 3 0 0 1 i1 1 c 4 c 3 0 1 0 v1 1 c 4 c 3 0 1 1 i2 1 c 4 c 3 1 0 0 v2 1 c 4 c 3 1 1 0 all four for calibrations, c [2:0] specifies the channel(s). sdi/rx checksum page select cmd . sdo/tx sdi/rx checksum data data data checksum read cmd . sdi/rx data data data checksum write cmd. sdi/rx checksum instruction page select instruction read command write command cs5484 ds981f2 29 6.2 hardware regist ers summary (page 0) address 2 ra[5:0] name description 1 dsp 3 host 3 default 0* 00 0000 config0 configuration 0 y y 0x 40 0000 1* 00 0001 config1 configuration 1 y y 0x 00 eeee 2 00 0010 reserved - 3* 00 0011 mask interrupt mask y y 0x 00 0000 4 00 0100 - reserved - 5* 00 0101 pc phase compensation control y y 0x 00 0000 6 00 0110 - reserved - 7* 00 0111 serialctrl uart control y y 0x 02 004d 8* 00 1000 pulsewidth energy pulse width y y 0x 00 0001 9* 00 1001 pulsectrl energy pulse control y y 0x 00 0000 10 00 1010 - reserved - 11 00 1011 - reserved - 12 00 1100 - reserved - 13 00 1101 - reserved - 14 00 1110 - reserved - 15 00 1111 - reserved - 16 01 0000 - reserved - 17 01 0001 - reserved - 18 01 0010 - reserved - 19 01 0011 - reserved - 20 01 0100 - reserved - 21 01 0101 - reserved - 22 01 0110 - reserved - 23 01 0111 status0 interrupt status n n 0x 80 0000 24 01 1000 status1 chip status 1 n n 0x 80 1800 25 01 1001 status2 chip status 2 n n 0x 00 0000 26 01 1010 - reserved - 27 01 1011 - reserved - 28 01 1100 - reserved - 29 01 1101 - reserved - 30 01 1110 - reserved - 31 01 1111 - reserved - 32 10 0000 - reserved - 33 10 0001 - reserved - 34* 10 0010 reglock register lock control n n 0x 00 0000 35 10 0011 - reserved - 36 10 0100 v1 peak v1 peak voltage n y 0x 00 0000 37 10 0101 i1 peak i1 peak current n y 0x 00 0000 38 10 0110 v2 peak v2 peak voltage n y 0x 00 0000 39 10 0111 i2 peak i2 peak current n y 0x 00 0000 40 10 1000 - reserved - 41 10 1001 - reserved - 42 10 1010 - reserved - 43 10 1011 - reserved - 44 10 1100 - reserved - 45 10 1101 - reserved - 46 10 1110 - reserved - 47 10 1111 - reserved - 48 11 0000 psdc phase sequence detection & control n y 0x 00 0000 49 11 0001 - reserved - 50 11 0010 - reserved - 51 11 0011 - reserved - 52 11 0100 - reserved - cs5484 30 ds981f2 53 11 0101 - reserved - 54 11 0110 - reserved - 55 11 0111 zx num num. zero crosses used for line freq. y y 0x00 0064 56 11 1000 - reserved - 57 11 1001 - reserved - 58 11 1010 - reserved - 59 11 1011 - reserved - 60 11 1100 - reserved - 61 11 1101 - reserved - 62 11 1110 - reserved - 63 11 1111 - reserved - notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. cs5484 ds981f2 31 6.3 software regist ers summary (page 16) address 2 ra[5:0] name description 1 dsp 3 host 3 default 0* 00 0000 config2 configuration 2 y y 0x 06 0200 1 00 0001 regchk register checksum n y 0x 00 0000 2 00 0010 i1 i1 instantaneous current n y 0x 00 0000 3 00 0011 v1 v1 instantaneous voltage n y 0x 00 0000 4 00 0100 p1 instantaneous power 1 n y 0x 00 0000 5 00 0101 p1 avg active power 1 n y 0x 00 0000 6 00 0110 i1 rms i1 rms current n y 0x 00 0000 7 00 0111 v1 rms v1 rms voltage n y 0x 00 0000 8 00 1000 i2 i2 instantaneous current n y 0x 00 0000 9 00 1001 v2 v2 instantaneous voltage n y 0x 00 0000 10 00 1010 p2 instantaneous power 2 n y 0x 00 0000 11 00 1011 p2 avg active power 2 n y 0x 00 0000 12 00 1100 i2 rms i2 rms current n y 0x 00 0000 13 00 1101 v2 rms v2 rms voltage n y 0x 00 0000 14 00 1110 q1 avg reactive power 1 n y 0x 00 0000 15 00 1111 q1 instantaneous reactive power 1 n y 0x 00 0000 16 01 0000 q2 avg reactive power 2 n y 0x 00 0000 17 01 0001 q2 instantaneous reactive power 2 n y 0x 00 0000 18 01 0010 - reserved - 19 01 0011 - reserved - 20 01 0100 s1 apparent power 1 n y 0x 00 0000 21 01 0101 pf1 power factor 1 n y 0x 00 0000 22 01 0110 - reserved - 23 01 0111 - reserved - 24 01 1000 s2 apparent power 2 n y 0x 00 0000 25 01 1001 pf2 power factor 2 n y 0x 00 0000 26 01 1010 - reserved - 27 01 1011 t temperature n y 0x 00 0000 28 01 1100 - reserved - 29 01 1101 p sum total active power n y 0x 00 0000 30 01 1110 s sum total apparent power n y 0x 00 0000 31 01 1111 q sum total reactive power n y 0x 00 0000 32* 10 0000 i1 dcoff i1 dc offset y y 0x 00 0000 33* 10 0001 i1 gain i1 gain y y 0x 40 0000 34* 10 0010 v1 dcoff v1 dc offset y y 0x 00 0000 35* 10 0011 v1 gain v1 gain y y 0x 40 0000 36* 10 0100 p1 off average active power 1 offset y y 0x 00 0000 37* 10 0101 i1 acoff i1 ac offset y y 0x 00 0000 38* 10 0110 q1 off average reactive power 1 offset y y 0x 00 0000 39* 10 0111 i2 dcoff i2 dc offset y y 0x 00 0000 40* 10 1000 i2 gain i2 gain y y 0x 40 0000 41* 10 1001 v2 dcoff v2 dc offset y y 0x 00 0000 42* 10 1010 v2 gain v2 gain y y 0x 40 0000 43* 10 1011 p2 off average active power 2 offset y y 0x 00 0000 44* 10 1100 i2 acoff i2 ac offset y y 0x 00 0000 45* 10 1101 q2 off average reactive power 2 offset y y 0x 00 0000 46 10 1110 - reserved - 47 10 1111 - reserved - 48 11 0000 - reserved - 49 11 0001 epsilon ratio of line to sample frequency n y 0x 01 999a 50* 11 0010 - reserved - 51* 11 0011 samplecount sample count n y 0x 00 0fa0 52 11 0100 - reserved - cs5484 32 ds981f2 53 11 0101 - reserved - 54* 11 0110 t gain temperature gain y y 0x 06 b716 55* 11 0111 t off temperature offset y y 0x d5 3998 56* 11 1000 - reserved - 57 11 1001 t settle filter settling time to conv. startup y y 0x 00 001e 58* 11 1010 load min no-load threshold y y 0x 00 0000 59* 11 1011 - reserved - 60* 11 1100 sys gain system gain n y 0x 50 0000 61 11 1101 time system time (in samples) n y 0x 00 0000 62 11 1110 - reserved - 63 11 1111 - reserved - notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. cs5484 ds981f2 33 6.4 software regist ers summary (page 17) address 2 ra[5:0] name description 1 dsp 3 host 3 default 0* 00 0000 v1sag dur v1 sag duration y y 0x 00 0000 1* 00 0001 v1sag level v1 sag level y y 0x 00 0000 2 00 0010 - reserved - 3 00 0011 - reserved - 4* 00 0100 i1over dur i1 overcurrent duration y y 0x 00 0000 5* 00 0101 i1over level i1 overcurrent level y y 0x 7f ffff 6 00 0110 - reserved - 7 00 0111 - reserved - 8* 00 1000 v2sag dur v2 sag duration y y 0x 00 0000 9* 00 1001 v2sag level v2 sag level y y 0x 00 0000 10 00 1010 - reserved - 11 00 1011 - reserved - 12* 00 1100 i2over dur i2 overcurrent duration y y 0x 00 0000 13* 00 1101 i2over level i2 overcurrent level y y 0x 7f ffff 14 00 1110 - reserved - 15 00 1111 - reserved - 16 01 0000 - reserved - 17 01 0001 - reserved - 18 01 0010 - reserved - 19 01 0011 - reserved - 20 01 0100 - reserved - 21 01 0101 - reserved - 22 01 0110 - reserved - 23 01 0111 - reserved - 24 01 1000 - reserved - 25 01 1001 - reserved - 26 01 1010 - reserved - 27 01 1011 - reserved - 28 01 1100 - reserved - 29 01 1101 - reserved - 30 01 1110 - reserved - 31 01 1111 - reserved - notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. cs5484 34 ds981f2 6.5 software regist ers summary (page 18) address 2 ra[5:0] name description 1 dsp 3 host 3 default 24* 01 1000 izx level zero-cross threshold for i-channel y y 0x 10 0000 25 01 1001 - reserved - 26 01 1010 - reserved - 27 01 1011 - reserved - 28* 01 1100 pulserate energy pulse rate y y 0x 80 0000 29 01 1101 - reserved - 30 01 1110 - reserved - 31 01 1111 - reserved - 32 10 0000 - reserved - 33 10 0001 - reserved - 34 10 0010 - reserved - 35 10 0011 - reserved - 36 10 0100 - reserved - 37 10 0101 - reserved - 38 10 0110 - reserved - 39 10 0111 - reserved - 40 10 1000 - reserved - 41 10 1001 - reserved - 42 10 1010 - reserved - 43* 10 1011 int gain rogowski coil integrator gain y y 0x14 3958 44 10 1100 - reserved - 45 10 1101 - reserved - 46* 10 1110 v1swell dur v1 swell duration y y 0x 00 0000 47* 10 1111 v1swell level v1 swell level y y 0x 7f ffff 48 11 0000 - reserved - 49 11 0001 - reserved - 50* 11 0010 v2swell dur v2 swell duration y y 0x 00 0000 51* 11 0011 v2swell level v2 swell level y y 0x 7f ffff 52 11 0100 - reserved - 53 11 0101 - reserved - 54 11 0110 - reserved - 55 11 0111 - reserved - 56 11 1000 - reserved - 57 11 1001 - reserved - 58* 11 1010 vzx level zero-cross threshold for v-channel y y 0x 10 0000 59 11 1011 - reserved - 60 11 1100 - reserved - 61 11 1101 - reserved - 62* 11 1110 cyclecount line cycle count n y 0x 00 0064 63* 11 1111 scale i-channel gain calibration scale value y y 0x 4c cccc notes: (1) warning: do not write to unpublished or reserved register locations. (2) * registers with checksum protection. (3) registers that can be set to write protect from dsp and/or host. cs5484 ds981f2 35 6.6 register descriptions 1. ?default? = bit states after power-on or reset 2. do not write a ?1? to any unpublished regi ster bit or to a bit published as ?0?. 3. do not write a ?0? to any bit published as ?1?. 4. do not write to any unpublished register address. 6.6.1 configuration 0 (config0) ? page 0, address 0 default = 0x40 0000 tsel selects between voltage channel2 and temperature. 0 = selects voltage channel 2 (default) 1 = selects temperature sensor [22] reserved. icpuclk cpu clock inversion control. 0 = cpu clock is same as mclk (default) 1 = invert cpu clock to pin (cpu clock is inversion of mclk) cuclk_on enable cpuclk to pad. 0 = disable cpuclk to pin (default) 1 = enable cpuclk to pin [19:15] reserved. v2cap[1:0] select the internal samp ling capacitor size for v2 channel. must be set to 00 for voltage measurement. 00 = v2 used for voltage measurement (default) 01 = v2 used for temperature measurement 10 = reserved 11 = reserved [12:9] reserved. int_pol interrupt polarity. 0 = active low (default) 1 = active high i2pga[1:0] select pga gain for i2 channel. 00 = 10x gain (default) 10 = 50x gain i1pga[1:0] select pga gain for i1 channel. 00 = 10x gain (default) 10 = 50x gain [3] reserved. 23 22 21 20 19 18 17 16 tsel 1 icpuclk cpuclk_on - - - - 15 14 13 12 11 10 9 8 - v2cap[1] v2cap[0] 0 0 - - int_pol 76543210 i2pga[1] i2pga[0] i1pga[1] i1 pga[0] - no_osc izx_ch vzx_ch cs5484 36 ds981f2 no_osc disable crystal oscillator (m aking xin a logic-level input). 0 = crystal oscillator enabled (default) 1 = crystal oscillator disabled izx_ch select current channe l for zero-cross detect. 0 = selects current channel 1 fo r zero-cross detect (default) 1 = selects current channe l 2 for zero-cross detect vzx_ch selects voltage channe l for zero-cross detect. 0 = selects voltage channel 1 fo r zero-cross detect (default) 1 = selects voltage channel 2 for zero-cross detect 6.6.2 configuration 1 (config1) ? page 0, address 1 default = 0x00 eeee epg4_on enable epg4 block. 0 = disable energy pulse generation block 4 (default) 1 = enable energy pulse generation 4 epg3_on enable epg3 block. 0 = disable energy pulse generation block 3 (default) 1 = enable energy pulse generation block 3 epg2_on enable epg2 block. 0 = disable energy pulse generation block 2 (default) 1 = enable energy pulse generation block 2 epg1_on enable epg1 block. 0 = disable energy pulse generation block 1 (default) 1 = enable energy pulse generation block 1 do4_od allow the do4 pin to be an open-drain output. 0 = normal output (default) 1 = open-drain output do3_od allow the do3 pin to be an open-drain output. 0 = normal output (default) 1 = open-drain output do2_od allow the do2 pin to be an open-drain output. 0 = normal output (default) 1 = open-drain output do1_od allow the do1 pin to be an open-drain output. 0 = normal output (default) 1 = open-drain output 23 22 21 20 19 18 17 16 epg4_on epg3_on epg2_ on epg1_on do4_od do3_od do2_od do1_od 15 14 13 12 11 10 9 8 do4mode[3] do4mode[2] do4mode[ 1] do4mode[0] do3mode[3] do3m ode[2] do3mode[1] do3mode[0] 76543210 do2mode[3] do2mode[2] do2mode[ 1] do2mode[0] do1mode[3] do1m ode[2] do1mode[1] do1mode[0] cs5484 ds981f2 37 do4mode[3:0] output control for do4 pin. 0000 = energy pulse generation block 1 (epg1) output 0001 = energy pulse generation block 2 (epg2) output 0010 = energy pulse generation block 3 (epg3) output 0011 = energy pulse generation block 4 (epg4) output 0100 = p1 sign 0101 = p2 sign 0110 = p sum sign 0111 = q1 sign 1000 = q2 sign 1001 = q sum sign 1010 = reserved 1011 = v1/v2 zero-crossing 1100 = i1/i2 zero-crossing 1101 = reserved 1110 = hi-z, pin not driven (default) 1111 = interrupt do3mode[3:0] output control for do3 pin. 0000 = energy pulse generation block 1 (epg1) output 0001 = energy pulse generation block 2 (epg2) output 0010 = energy pulse generation block 3 (epg3) output 0011 = energy pulse generation block 4 (epg4) output 0100 = p1 sign 0101 = p2 sign 0110 = p sum sign 0111 = q1 sign 1000 = q2 sign 1001 = q sum sign 1010 = reserved 1011 = v1/v2 zero-crossing 1100 = i1/i2 zero-crossing 1101 = reserved 1110 = hi-z, pin not driven (default) 1111 = interrupt do2mode[3:0] output control for do2 pin. 0000 = energy pulse generation block 1 (epg1) output 0001 = energy pulse generation block 2 (epg2) output 0010 = energy pulse generation block 3 (epg3) output 0011 = energy pulse generation block 4 (epg4) output 0100 = p1 sign 0101 = p2 sign 0110 = p sum sign 0111 = q1 sign 1000 = q2 sign 1001 = q sum sign 1010 = reserved 1011 = v1/v2 zero-crossing 1100 = i1/i2 zero-crossing 1101 = reserved 1110 = hi-z, pin not driven (default) 1111 = interrupt cs5484 38 ds981f2 do1mode[3:0] output control for do1 pin. 0000 = energy pulse generation block 1 (epg1) output 0001 = energy pulse generation block 2 (epg2) output 0010 = energy pulse generation block 3 (epg3) output 0011 = energy pulse generation block 4 (epg4) output 0100 = p1 sign 0101 = p2 sign 0110 = p sum sign 0111 = q1 sign 1000 = q2 sign 1001 = q sum sign 1010 = reserved 1011 = v1/v2 zero-crossing 1100 = i1/i2 zero-crossing 1101 = reserved 1110 = hi-z, pin not driven (default) 1111 = interrupt 6.6.3 configuration 2 (config2) ? page 16, address 0 default = 0x06 0200 [23] reserved. pos positive energy only. supp ress negative values in p1 avg and p2 avg . if a negative val- ue is calculated, a zero result will be stored. 0 = positive and negative energy (default) 1 = positive energy only [21:15] reserved. apcm selects the apparent power calculation method. 0 = vx rms ? ix rms (default) 1 = sqrt(px avg 2 + qx avg 2 ) [13] reserved. zx_lpf enable lpf in zero-cross detect. 0 = lpf disabled (default) 1 = lpf enabled avg_mode select averaging mode for low-rate calculations. 0 = use samplecount (default) 1 = use cyclecount reg_csum_off disable checksum on critical registers. 0 = enable checksum on critical registers (default) 1 = disable checksum on critical registers 23 22 21 20 19 18 17 16 -pos- - - 1 1- 15 14 13 12 11 10 9 8 - apcm - zx_lpf avg_mode reg_csum_off afc i2flt[1] 76543 2 10 i2flt[0] v2flt[1] v2flt[0] i1flt[1] i1flt[0] v1flt[1] v1flt[0] iir_off cs5484 ds981f2 39 afc enables automatic line frequency measurement which sets epsilon every time a new line frequency measurement completes. epsilon is used to control the gain of 90 de- gree phase shift integrator used in quadrature power calculations. 0 = disable automatic line frequency measurement 1 = enable automatic line fr equency measurement (default) i2flt[1:0] filter enable for current channel 2. 00 = no filter (default) 01 = high-pass filter (hpf) on current channel 2 10 = phase-matching filter (pmf) on current channel 2 11 = rogowski coil integrator on current channel 2 v2flt[1:0] filter enable for voltage channel 2/temperature. 00 = no filter (default) 01 = high-pass filter (hpf) on voltage channel 2 10 = phase-matching filter (pmf) on voltage channel 2 11 = reserved i1flt[1:0] filter enable for current channel 1. 00 = no filter (default) 01 = high-pass filter (hpf) on current channel 1 10 = phase-matching filter (pmf) on current channel 1 11 = rogowski coil integrator on current channel 1 v1flt[1:0] filter enable for voltage channel 1. 00 = no filter (default) 01 = high-pass filter (hpf) on voltage channel 1 10 = phase-matching filter (pmf) on voltage channel 1 11 = reserved iir_off bypass iir filter. 0 = do not bypass iir filter (default) 1 = bypass iir filter cs5484 40 ds981f2 6.6.4 phase compensation (pc) ? page 0, address 5 default = 0x00 0000 cpcc2[1:0] coarse phase compensation control for i2 and v2. 00 = no extra delay 01 = 1 owr delay in current channel 2 10 = 1 owr delay in voltage channel 2 11 = 2 owr delay in voltage channel 2 cpcc1[1:0] coarse phase compensation control for i1 and v1. 00 = no extra delay 01 = 1 owr delay in current channel 1 10 = 1 owr delay in voltage channel 1 11 = 2 owr delay in voltage channel 1 [19:18] reserved. fpcc2[8:0] fine phase compensation control for i2 and v2. sets a delay in current, relative to voltage. resolution: 0.008789 at 50hz an d 0.010547 at 60hz (owr = 4000) fpcc1[8:0] fine phase compensation control for i1 and v1. sets a delay in current, relative to voltage. resolution: 0.008789 at 50hz an d 0.010547 at 60hz (owr = 4000) 6.6.5 uart control (serialctrl) ? page 0, address 7 default = 0x02 004d [23:19] reserved. rx_pu_off disable the pull-up resistor on the rx input pin. 0 = pull-up resistor enabled (default) 1 = pull-up resistor disabled rx_csum_off disable the checksum on serial port data. 0 = enable checksum 1 = disable checksum (default) [16] reserved. br[15:0] baud rate (serial bit rate). br[15:0] = baud rate x (524,288/mclk) 23 22 21 20 19 18 17 16 cpcc2[1] cpcc2[0] cpcc1[1] cpcc1[0] - - fpcc2[8] fpcc2[7] 15 14 13 12 11 10 9 8 fpcc2[6] fpcc2[5] fpcc2[4] fpcc2[3] fpcc2[2] fpcc2[1] fpcc2[0] fpcc1[8] 76543210 fpcc1[7] fpcc1[6] fpcc1[5] fpcc1[4] fpcc1[3] fpcc1[2] fpcc1[1] fpcc1[0] 23 22 21 20 19 18 17 16 - - - - - rx_pu_off rx_csum_off - 15 14 13 12 11 10 9 8 br[15] br[14] br[13] br[12] br[11] br[10] br[9] br[8] 765432 10 br[7] br[6] br[5] br[4] br[3] br[2] br[1] br[0] cs5484 ds981f2 41 6.6.6 pulse output width (pulsewidth) ? page 0, address 8 default = 0x00 0001 (265.6s at owr = 4khz) pulsewidth sets the energy pulse frequency range and the duration of energy pulses. the actual pulse duration is 250s plus the contents of pulsewidth divided by 64,000. pulsewidth is an inte- ger in the range of 1 to 65,535. [23:20] reserved. freq_rng[3:0] energy pulse ( pulserate ) frequency range for 0.1% resolution. 0000 = freq. range: 2khz?0.238hz (default) 0001 = freq. range: 1khz?0.1192hz 0010 = freq. range: 500 hz?0.0596hz 0011 = freq. range: 250hz?0.0298hz 0100 = freq. range: 125 hz?0.0149hz 0101 = freq. range: 62.5 hz?0.00745hz 0110 = freq. range: 31.25hz?0.003725hz 0111 = freq. range: 15.625hz?0.0018626hz 1000 = freq. range: 7.8125hz?0.000931323hz 1001 = freq. range: 3.90625hz?0.000465661hz 1010 = reserved ... 1111 = reserved pw[15:0] energy pulse width. 6.6.7 pulse output rate (pulserate) ? page 18, address 28 default= 0x80 0000 pulserate sets the full-scale frequency fo r the energy pulse outputs. for a 4 khz owr rate, the maximum pulse rate is 2khz. this is a two's complement value in the range of -1 ? value ? 1, with the binary point to the left of the msb. refer to section 5.5 energy pulse generation on page 22 for more information. 23 22 21 20 19 18 17 16 - - - - freq_rng[3] freq_rng[2] freq_rng[1] freq_rng[0] 15 14 13 12 11 10 9 8 pw[15] pw[14] pw[13] pw[12] pw[11] pw[10] pw[9] pw[8] 76543210 pw[7] pw[6] pw[5] pw[4] pw[3] pw[2] pw[1] pw[0] msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 42 ds981f2 6.6.8 pulse output control (pulsectrl) ? page 0, address 9 default = 0x00 0000 this register controls the input to t he energy pulse generation block (epgx). [23:16] reserved. epgxin[3:0] selects the input to the energy pulse generation block (epgx). 0000 = p1 avg (default) 0001 = p2 avg 0010 = p sum 0011 = q1 avg 0100 = q2 avg 0101 = q sum 0110 = s1 0111 = s2 1000 = s sum 1001 = unused ... 1111 = unused 6.6.9 register lock control (reglock) ? page 0, address 34 default = 0x00 0000 [23:13] reserved. dsp_lck[4:0] dsp_lck[4:0] = 0x16 sets the dsp lockable registers to be write protected from the cs5484 internal calculation engine. writing 0x09 unlocks the registers. [7:5] reserved. host_lck[4:0] host_lck[4:0] = 0x16 sets all the registers except reglock , status0 , status1 , and status2 to be write protected from the serial in terface. writing 0x09 unlocks the regis- ters. 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 epg4in[3] epg4in[2] epg4in[1] epg4in[ 0] epg3in[3] epg3in[2] epg3in[1] epg3in[0] 76543210 epg2in[3] epg2in[2] epg2in[1] epg2in[ 0] epg1in[3] epg1in[2] epg1in[1] epg1in[0] 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 - - - dsp_lck[4] dsp_lck[3] dsp _lck[2] dsp_lck[1] dsp_lck[0] 76543210 - - - host_lck[4] host_lck[3] host _lck[2] host_lck[1] host_lck[0] cs5484 ds981f2 43 6.6.10 phase sequence detection and control (psdc) ? page 0, address 48 default = 0x00 0000 done indicates valid count values reside in pscnt[6:0]. 0 = invalid values in pscnt[6:0]. (default) 1 = valid values in pscnt[6:0]. pscnt[6:0] registers the number of owr samples from the start ti me to the time when the next zero crossing is detected. [15:6] reserved. dir set the zero-crossing edge dire ction which will stop pscnt count. 0 = stop count at negative to positive zero-crossing - rising edge. (default) 1 = stop count at positive to nega tive zero-crossing - falling edge. code[4:0] write 10110 to this location to enable the phase sequence detection. 6.6.11 checksum of critical registers (regchk) ? page 16, address 1 default = 0x00 0000 this register contains the ch ecksum of critical registers. 23 22 21 20 19 18 17 16 done pscnt[6] pscnt[5] pscnt[4] psc nt[3] pscnt[2] pscnt[1] pscnt[0] 15 14 13 12 11 10 9 8 ------ -- 765432 10 - - dir code[4] code[3] code[2] code[1] code[0] msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5484 44 ds981f2 6.6.12 interrupt status (status0) ? page 0, address 23 default = 0x80 0000 the status0 register indicates a variety of conditions within the chip. writing a one to a status0 register bit will clear that bit. writ ing a zero to any bit has no effect. drdy data ready. during conversion, this bit indicates that low-rate results have been updated. it indicates completion of other host instruction and the reset sequence. crdy conversion ready. indicates that sample rate (output word rate) results have been updated. wof watchdog timer overflow. [20:19] reserved. mips mips overflow. sets when the calculation engine has not completed processing a sample before the next one arrives. v2swell(v1swell) voltage channel 2 (volt age channel 1) swell event detected. p2or (p1or) power out of range. sets when the measured power would cause the p2 ( p1 ) register to overflow. i2or (i1or) current out of range. set when the measured current would cause the i2 ( i1 ) register to overflow. v2or (v1or) voltage out of range. set when the measured voltage would cause the v2 ( v1 ) register to overflow. i2oc (i1oc) i2 ( i1 ) overcurrent. v2sag (v1sag) voltage channel 2 (volt age channel 1) sag event detected. tup temperature updated. indicates when the temperature register ( t ) has been updated. fup frequency updated. indicates the epsilon register has been updated. ic invalid command has been received. rx_csum_err received data checksum error. sets to one automatically if checksum error is detected on serial port received data. [1] reserved. rx_to sdi/rx time out. sets to one automatically wh en sdi/rx time out occurs. 23 22 21 20 19 18 17 16 drdy crdy wof - - mips v2swell v1swell 15 14 13 12 11 10 9 8 p2or p1or i2or i1or v2or v1or i2oc i1oc 76543 2 10 v2sag v1sag tup fup ic rx_csum_err - rx_to cs5484 ds981f2 45 6.6.13 interrupt mask (mask) ? page 0, address 3 default = 0x00 0000 the mask register is used to cont rol the activation of the int pin. writing a '1' to a mask register bit will allow the corresponding status0 register bit to activate the int pin when set. [23:0] enable/disable (mask) interrupts. 0 = interrupt disabled (default) 1 = interrupt enabled 6.6.14 chip status 1 (status1) ? page 0, address 24 default = 0x80 1800 this register indicates a variety of conditions within the chip. [23:16] reserved. lcom[7:0] indicates the value of the last serial command executed. v2od (v1od) modulator oscillation has been detected in the vo ltage2 (voltage1) adc. i2od (i1od) modulator oscillati on has been detected in th e current2 (c urrent1) adc. 23 22 21 20 19 18 17 16 drdy crdy wof - - mips v2swell v1swell 15 14 13 12 11 10 9 8 p2or p1or i2or i1or v2or v1or i2oc i1oc 76543 2 10 v2sag v1sag tup fup ic rx_csum_err - rx_to 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 lcom[7] lcom[6] lcom[5] lcom[4] lcom[3] lcom[2] lcom[1] lcom[0] 76543210 - - - - v2od v1od i2od i1od cs5484 46 ds981f2 6.6.15 chip status 2 (status2) ? page 0, address 25 default = 0x00 0000 this register indicates a variety of conditions within the chip. [23:6] reserved. qsum_sign indicates the sign of the value contained in q sum . 0 = positive value 1 = negative value q2_sign indicates the sign of the value contained in q2 avg . 0 = positive value 1 = negative value q1_sign indicates the sign of the value contained in q1 avg . 0 = positive value 1 = negative value psum_sign indicates the sign of the value contained in p sum . 0 = positive value 1 = negative value p2_sign indicates the sign of the value contained in p2 avg . 0 = positive value 1 = negative value p1_sign indicates the sign of the value contained in p1 avg . 0 = positive value 1 = negative value 23 22 21 20 19 18 17 16 -------- 15 14 13 12 11 10 9 8 -------- 76543210 - - qsum_sign q2_sign q1_sign psum_sign p2_sign p1_sign cs5484 ds981f2 47 6.6.16 line to sample frequency ratio (epsilon) ? page 16, address 49 default = 0x01 999a (0.0125 or 50hz/4.0khz) epsilon is the ratio of the input line frequency to the owr. it can either be written by the application program or calculated automatically fr om the line frequency (from the voltage channel 1 input) using the afc bit in the config2 register. it is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.17 no-load threshold (load min ) ? page 16, address 58 default = 0x00 0000 load min is used to set the no-load thre shold for the anti -creep function. when the magnitudes of p sum and q sum are less than load min , p sum and q sum are forced to zero. when the magnitude of s sum is less than load min , s sum is forced to zero. load min is a two?s complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.18 sample count (samplecount) ? page 16, address 51 default = 0x00 0fa0 (4000) determines the number of owr samples to use in calculating low-rate results. samplecount ( n ) is an integer in the range of 100 to 8,388, 607. values less than 100 should not be used. 6.6.19 cycle count (cyclecount) ? page 18, address 62 default = 0x00 0064 (100) determines the number of half-line cycles to use in calcul ating low-rate results when the cs5484 is in line-cy- cle synchronized averaging mode. cyclecount is an integer in the range of 1 to 8,388,607. zero should not be used. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5484 48 ds981f2 6.6.20 filter settling time for conversion startup (t settle ) ? page 16, address 57 default = 0x00 001e (30) sets the number of owr samples that will be used to a llow filters to settle at th e beginning of conversion and calibration commands. this is an integer in the range of 0 to 16,777,215 samples. 6.6.21 system gain (sys gain ) ? page 16, address 60 default = 0x50 0000 (1.25) system gain ( sys gain ) is applied to all channels. by default, sys gain = 1.25 but can be finely adjusted to compensate for voltage reference error. it is a two's complement value in the range of -2.0 ? value ? 2.0, with the binary point to the right of the second msb. val- ues should be kept within 5% of 1.25. 6.6.22 rogowski coil integrator gain (int gain ) ? page 18, address 43 default = 0x14 3958 gain for the rogowski coil integrator. this must be programmed accordingly for 50hz and 60hz (0.158 for 50hz, 0.1875 for 60hz). this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.23 system time (time) ? page 16, address 61 default = 0x00 0000 system time ( time ) is measured in owr samples. this is an unsigned integer in the range of 0 to 16 ,777,215 samples. at ow r = 4.0khz, owr will overflow every 1 hour, 9 minutes, 54 seconds. time can be used by the application to manage real-time events. msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 1 )2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5484 ds981f2 49 6.6.24 voltage 1 sag duration (v1sag dur ) ? page 17, address 0 default = 0x00 0000 voltage sag duration, v1sag dur , determines the count of owr sample s utilized to determine a sag event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. 6.6.25 voltage 1 sag level (v1sag level ) ? page 17, address 1 default = 0x00 0000 voltage sag level, v1sag level , establishes an input level below which a sag event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.26 current 1 overcurrent duration (i1over dur ) ? page 17, address 4 default = 0x00 0000 overcurrent duration, i1over dur , determines th e count of owr samples utilized to determine an overcurrent event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. 6.6.27 current 1 overcurrent level (i1over level ) ? page 17, address 5 default = 0x7f ffff overcurrent level, i1over level , establishes an input level above which an overcurrent event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 50 ds981f2 6.6.28 voltage 2 sag duration (v2sag dur ) ? page 17, address 8 default = 0x00 0000 voltage sag duration, v2sag dur , determines the count of owr sample s utilized to determine a sag event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. 6.6.29 voltage 2 sag level (v2sag level ) ? page 17, address 9 default = 0x00 0000 voltage sag level, v2sag level , establishes an input level below which a sag event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.30 current 2 overcurrent duration (i2over dur ) ? page 17, address 12 default = 0 x00 0000 overcurrent duration, i2over dur , determines th e count of owr samples utilized to determine an overcurrent event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. 6.6.31 current 2 overcurrent level (i2over level ) ? page 17, address 13 default = 0x7f ffff overcurrent level, i2over level , establishes an input level above whic h an overcurrent event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 ds981f2 51 6.6.32 voltage 1 swell duration (v1swell dur ) ? page 18, address 46 default = 0x00 0000 voltage swell duration, v1swell dur , determines the count of owr samp les utilized to determine a swell event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. 6.6.33 voltage 1 swell level (v1swell level ) ? page 18, address 47 default = 0x7f ffff voltage swell level, v1swell level , establishes an input level above which a swell event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.34 voltage 2 swell duration (v2swell dur ) ? page 18, address 50 default = 0x00 0000 voltage swell duration, v2swell dur , determines the count of owr samp les utilized to determine a swell event. these are integers in the range of 0 to 8,388,60 7 samples. a value of zero disables the feature. 6.6.35 voltage 2 swell level (v2swell level ) ? page 18, address 51 default = 0x7f ffff voltage swell level, v2swell level , establishes an input level above which a swell event is triggered. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 52 ds981f2 6.6.36 instantaneous current 1 (i1) ? page 16, address 2 default = 0x00 0000 i1 contains instantaneous current measurements for current channel 1. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.37 instantaneous voltage 1 (v1) ? page 16, address 3 default = 0x00 0000 v1 contains instantaneous voltage measurements for voltage channel 1. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.38 instantaneous active power 1 (p1) ? page 16, address 4 default = 0x00 0000 p1 contains instantaneous power measuremen ts for current and voltage channels 1. values in registers i1 and v1 are multiplied to generate this value. th is is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.39 active power 1 (p1 avg ) ? page 16, address 5 default = 0x00 0000 instantaneous power is averaged over each low-rate interval ( samplecount samples) and then added with power offset ( p off ) to compute active power ( p avg ). this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 ds981f2 53 6.6.40 rms current 1 (i1 rms ) ? page 16, address 6 default = 0x00 0000 i1 rms contains the root mean square (rms) values of i1 , calculated during each low-rate interval. this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. 6.6.41 rms voltage 1 (v1 rms ) ? page 16, address 7 default = 0x00 0000 v1 rms contains the root mean square (rms) value of v1 , calculated during each low-rate interval. this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. 6.6.42 instantaneous current 2 (i2) ? page 16, address 8 default = 0x00 0000 i2 contains instantaneous current me asurements for current channel 2. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.43 instantaneous voltage 2 (v2) ? page 16, address 9 default = 0x00 0000 v2 contains instantaneous voltage measurements for voltage channel 2. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 54 ds981f2 6.6.44 instantaneous active power 2 (p2) ? page 16, address 10 default = 0x00 0000 p2 contains instantaneous power measuremen ts for current and voltage channels 2. values in registers i2 and v2 are multiplied to generate this value. th is is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.45 active power 2 (p2 avg ) ? page 16, address 11 default = 0x00 0000 instantaneous power is averaged over each low-rate interval ( samplecount samples) to compute active pow- er ( p2 avg ). this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.46 rms current 2 (i2 rms ) ? page 16, address 12 default = 0x00 0000 i2 rms contains the root mean square (rms) value of i2 , calculated during each low-rate interval. this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. 6.6.47 rms voltage 2 (v2 rms ) ? page 16, address 13 default = 0x00 0000 v2 rms contains the root mean square (rms) value of v2 , calculated during each low-rate interval. this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 cs5484 ds981f2 55 6.6.48 reactive power 1 (q1 avg ) ? page 16, address 14 default = 0x00 0000 reactive power 1 ( q1 avg ) is q1 averaged over each low-rate interval ( samplecount samples) and corrected by q off . this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.49 instantaneous quadrature power 1 (q1) ? page 16, address 15 default = 0x00 0000 instantaneous qu adrature power, q1 , the product of v1 shifted 90 degrees and i1 . this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.50 reactive power 2 (q2 avg ) ? page 16, address 16 default = 0x00 0000 reactive power 2 ( q2 avg ) is q2 averaged over each low-rate interval ( samplecount samples). this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.51 instantaneous quadrature power 2 (q2) ? page 16, address 17 default = 0x00 0000 instantaneous qu adrature power, q2 , the product of v2 shifted 90 degrees and i2 . this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 56 ds981f2 6.6.52 peak current 1 (i1 peak ) ? page 0, address 37 default = 0x00 0000 peak current1 ( i1 peak ) contains the value of the instantaneous current 1 sample with the greatest magnitude detected during the last low-rate interval. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.53 peak voltage 1 (v1 peak ) ? page 0, address 36 default = 0x00 0000 peak voltage 1 ( v1 peak ) contains the value of the instantaneous voltage 1 sample with the greatest magni- tude detected during the last low-rate interval. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.54 apparent power 1 (s1) ? page 16, address 20 default = 0x00 0000 apparent power 1 ( s1 ) is the product of v1 rms and i1 rms or sqrt( p1 avg 2 + q1 avg 2 ). this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.55 power factor 1 (pf1) ? page 16, address 21 default = 0x00 0000 power factor 1 ( pf1 ) is calculated by dividing active power 1 ( p1 avg ) by apparent power 1 ( s1 ). the sign is determined by the active power ( p1 avg ) sign. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 ds981f2 57 6.6.56 peak current 2 (i2 peak ) ? page 0, address 39 default = 0x00 0000 peak current, i2 peak , contains the value of the instantaneous current 2 sample with the greatest magnitude detected during the last low-rate interval. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.57 peak voltage 2 (v2 peak ) ? page 0, address 38 default = 0x00 0000 peak voltage, v2 peak , contains the value of the instantaneous vo ltage 2 sample with the greatest magnitude detected during the last low-rate interval. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.58 apparent power 2 (s2) ? page 16, address 24 default = 0x00 0000 apparent power 2 ( s2 ) is the product of v2 rms and i2 rms or sqrt( p2 avg 2 + q2 avg 2 ). this is an unsigned value in the range of 0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.59 power factor 2 (pf2) ? page 16, address 25 default = 0x00 0000 power factor 2 ( pf2 ) is calculated by dividing active power 2 ( p2 avg ) by apparent power 2 ( s2 ). the sign is determined by the active power ( p2 avg ) sign. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 58 ds981f2 6.6.60 temperature (t) ? page 16, address 27 default = 0x00 0000 t contains results from the on- chip temperature measurement. by default, t uses the celsius scale and is a two's complement value in the range of -128.0 ? value ? 128.0 (c), with the binary point to the right of bit 16. t can be rescaled by the application using the t gain and t off registers. 6.6.61 total active power (p sum ) ? page 16, address 29 default = 0x00 0000 p sum =p1 avg +p2 avg this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.62 total apparent power (s sum ) ? page 16, address 30 default = 0x00 0000 s sum =s1+s2 this is an unsigned value in the range of 0.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.63 total reactive power (q sum ) ? page 16, address 31 default = 0x00 0000 q sum =q1 avg +q2 avg this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. msb lsb -(2 7 )2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 cs5484 ds981f2 59 6.6.64 dc offset for current (i1 dcoff , i2 dcoff ) ? page 16, address 32, 39 default = 0x00 0000 dc offset registers i1 dcoff and i2 dcoff are initialized to zero on reset. during dc offs et calibration, selected registers are written with the inverse of the dc offset measured. the application program can also write the dc offset register values. these are two' s complement values in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.65 dc offset for voltage (v1 dcoff , v2 dcoff ) ? page 16, address 34, 41 default = 0x00 0000 dc offset registers v1 dcoff and v2 dcoff are initialized to zero on reset. during dc offset calibration, select- ed registers are written with the inve rse of the dc offset measured. the application program can also write the dc offset register values. these are two's complement values in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.66 gain for current (i1 gain , i2 gain ) ? page 16, address 33, 40 default = 0x40 0000 (1.0) gain registers i1 gain and i2 gain are initialized to 1.0 on reset. during gain calibrati on, selected register are written with the multiplicative invers e of the gain measured. these are unsigned fixed-point values in the range of 0 ? value ? 4.0, with the binary point to the right of the second msb. 6.6.67 gain for voltage (v1 gain , v2 gain ) ? page 16, address 35, 42 default = 0x40 0000 (1.0) gain registers v 1 gain and v2 gain are initialized to 1.0 on reset. during gain calibrati on, selected registers are written with the multiplicative invers e of the gain measured. these are unsigned fixed-point values in the range of 0 ? value ? 4.0, with the binary point to the right of the second msb. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 msb lsb 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 ..... 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 cs5484 60 ds981f2 6.6.68 average active power offset (p1 off , p2 off ) ? page 16, address 36, 43 default = 0x00 0000 average active power offset p1 off ( p2 off ) is added to averaged power to yield p1 avg ( p2 avg ) register re- sults. it can be used to reduce systematic energy errors. these are two's complement values in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.69 average reactive offset (q1 off , q2 off ) ? page 16, address 38, 45 default = 0x00 0000 average reactive power offset q1 off ( q2 off ) is added to averaged reactive power to yield q1 avg ( q2 avg ) register results. it can be used to reduce systematic energy errors. these are two's complement values in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. 6.6.70 ac offset for current (i1 acoff , i2 acoff ) ? page 16, address 37, 44 default = 0x00 0000 ac offset registers i1 acoff and i2 acoff are initialized to zero on reset. they are used to reduce systematic errors in the rms results.these are unsigned values in the range of 0 ? value ? 1.0, with the binary point to the left of the msb. 6.6.71 temperature gain (t gain ) ? page 16, address 54 default = 0x 06 b716 register t gain is used to scale the temperature register ( t ), and is an unsigned fixed-point value in the range of 0.0 ? value ? 256.0, with the binary point to the right of bit 16. register t can be rescaled by the application using the t gain and t off registers. refer to section 7.3 tem- perature sensor calibration on page 64 for more information. msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 ..... 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2 -24 msb lsb 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 cs5484 ds981f2 61 6.6.72 temperature offset (t off ) ? page 16, address 55 default = 0x d5 3998 register t off is used to offset the temperature register ( t ), and is a two's complement value in the range of -128.0 ? value ? 128.0 (c), with the binary point to the right of bit 16. register t can be rescaled by the application using the t gain and t off registers. refer to section 7.3 tem- perature sensor calibration on page 64 for more information. 6.6.73 calibration scale (scale) ? page18, address 63 default = 0 x4c cccc (0.6) the scale register is used in the gain calibration to set t he level of calibrate d results of i-channel rms. during gain calibration, the ix rms results register is divided into the scale register. the quotient is put into the ix gain register. this is a two's complement value in the range of -1.0 ? value ? 1.0, with the binary point to the right of the msb. negative values are not used. 6.6.74 v-channel zero-crossing threshold (vzx level ) ? page 18, address 58 default = 0x10 0000 (0.125) vzx level is the level that the peak instantaneous voltag e must exceed for the zero-crossing detection to function. this is a two's complement value in the range of -1.0 ? value<1.0, with the binary point to the right of the msb. negative values are not used. 6.6.75 i-channel zero-crossing threshold (izx level ) ? page 18, address 24 default = 0x10 0000 (0.125) izx level is the level that the peak instant aneous current must exceed for the zero-crossing detection to func- tion. this is a two's compleme nt value in the range of -1.0 ? value<1.0, with the binary point to the right of the msb. negative values are not used. 6.6.76 zero-crossing number (zx num ) ? page 0, address 55 default = 0x00 0064 (100) zx num is the number of zero crossings used for line frequ ency measurement. it is an integer in the range of 1 to 8,388,607. zero should not be used. msb lsb -(2 7 )2 6 2 5 2 4 2 3 2 2 2 1 2 0 ..... 2 -10 2 -11 2 -12 2 -13 2 -14 2 -15 2 -16 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb -(2 0 )2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 ..... 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 msb lsb 2 23 2 22 2 21 2 20 2 19 2 18 2 17 2 16 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 cs5484 62 ds981f2 7. system calibration component tolerances, residual adc offset, and system noise require a meter that needs to be calibrated before it meets a specific accuracy requirement. the cs5484 provides an on-chip calibration algorithm to operate the system calibration quickly and easily. benefiting from the excellent linearity and low noise level of the cs5484, normally a cs5484 meter only needs one calibration at a single load point to achieve accurate measurements over the full load range. 7.1 calibration in general the cs5484 provides dc offset and gain calibration that can be applied to the instantaneous voltage and current measurements and ac offset calibration, which can be applied to the voltage and current rms calculations. since the voltage and current channels have independent offset and gain registers, offset and gain calibration can be performed on any channel independently. the data flow of the calibration is shown in figure 23 . note that in figure 23 the ac offset registers and gain registers affect the output results differently than the dc offset registers. the dc offset and gain values are applied to the voltage/current signals early in the signal path; the dc offset register and gain register values affect all cs5484 results. this is not true for the ac offset correction. the ac offs et registers only affect the results of the rms voltage and current calculations. the cs5484 must be operating in its active state and ready to accept valid co mmands. refer to section 6.1.2 instructions on page 27 for different calibration commands. the value in the samplecount register determines the number ( n ) of output word rate (owr) samples that are averaged during a calibration. the calibration procedure takes the time of n + t settle owr samples. as n is increased, the calibration takes more time, but the accuracy of the calibration results tends to increase. the drdy bit in the status0 register will be set at the completion of calibration commands. if an overflow occurs during calibration, other status0 bits may be set as well. 7.1.1 offset calibration during offset calibrations, no line voltage or current should be applied to the meter; the differential signal on voltage inputs v1in (v2in) or current inputs iin1 (iin2) of the cs5484 should be 0v. 7.1.1.1 dc offset calibration the dc offset calibration command measures and averages dc values read on specified voltage or current channels at zero input and stores the inverse result in the associated offset registers. this dc offset will be added to instanta neous measurements in subsequent conversions, removing the offset. the gain register for the channel being calibrated should be set to 1.0 prior to performing dc offset calibration. dc offset calibration is not required if the high-pass filter is enabled on that channel because the dc component will be removed by the high-pass filter.* v rms * , i rms * registers in modulator filter n ? * denotes readable/writable register ? applies only to the current path (i1, i2) ?? n ? n -1 ? n dc rms -1 rms 0.6( scale * ? ) v * , i * , p * , q * registers i gain * , v gain * registers i dco ff * , v dcoff * registers i acoff * ? register figure 23. calibration data flow cs5484 ds981f2 63 7.1.1.2 ac offset calibration the ac offset calibration command measures the residual rms values on the current channel at zero input and stores the squared result in the associated ac offset register. this ac offset will be subtracted from rms measurements in subsequent conversions, removing the ac offset on the associated current channel. the ac offset register for the channel being calibrated should first be cleared prior to performing the calibration. the high-pass filter should be enabled if ac offset calibration is used. it is recommended that t settle be set to 2000 ms before performing an ac offset calibration. note that the ac offset register holds the square of rms value measured during calibration. therefore, it can hold a maximum rms noise of . this is the maximum rms noise that ac offset correction can remove. 7.1.2 gain calibration prior to executing the gain calibration command, gain registers for any path to be calibrated ( vx gain , ix gain ) should be set to 1.0, and t settle should be set to 2000 ms. for gain calibration, a reference signal must be applied to the meter. du ring gain calibration, the voltage rms result register ( vx rms ) is divided into 0.6, and the current rms result register ( ix rms ) is divided into the scale register. the quotient is put into the associated gain register. the gain calibration algorithm attempts to adjust the gain register ( vx gain , ix gain ) such that the voltage rms result register ( vx rms ) equals 0.6, and the current rms result register ( ix rms ) equals the scale register. note that for the gain calibration, there are limitations on choosing the reference level and the scale register value. using a reference or a scale that is too large or too small can cause register overflow during calibration or later during normal operation. either condition can set status register bits i1or (i2or) v1or (v2or). the maximum value that the gain register can attain is four. using inappropriate reference levels or scale values may also cause the cs5484 to attempt to set the gain register higher than four, therefore the gain calibration result will be invalid. the scale register is 0.6 by default. the maximum voltage (u max volts) and current (i max amps) of the meter should be used as the reference signal level if the scale register is 0.6. after gain calibration, 0.6 of the vx rms ( ix rms ) register represents u max volts (i max amps) for the line voltage (load current); 0.36 of the px avg , qx avg , or sx register represents u max i max watts, vars, or vas for the active, reactive, or apparent power. if the calibration is performed with u max volts and i cal amps and i cal cs5484 64 ds981f2 3) accumulate multip le readings of the pf1 or pf2 register. 4) calculate the average power factor, pf avg . 5) calculate phase offset = arccos(pf avg ) - 60. 6) if the phase offset is negative, then the delay should be added only to the current channel. otherwise, add more delay to the voltage channel than to the current channel to compensate for a positive phase offset. once the phase offset is known, the cpccx and fpccx bits for that channel are calculated and programmed in the pc register. cpccx bits are used if either: ? the phase offset is more than 1 output word rate (owr) sample. ? more delay is needed on the voltage channel. the compensation resolution is 0.008789 at 50hz and 0.010547 at 60hz at an owr of 4000hz. 7.3 temperature sensor calibration temperature sensor calibration involves the adjustment of two parameters: temperature gain ( t gain ) and temperature offset (t off ). before calibration, t gain must be set to 1.0 (0x 01 0000), and t off must be set to 0.0 (0x 00 0000). 7.3.1 temperature offset and gain calibration to obtain the optimal temperature offset (t off ) register value and temperature (t gain ) register value, it is necessary to measure the temperature ( t ) register at a minimum of two points (t1 and t2) across the meter operating temperature range. the two temperature points must be far enough apart to yield reasonable accuracy, for example 25 c and 85 c. obtain a linear fit of these points ( ), where the slope (m) and intercept (b) can be obtained. figure 24. t register vs. force temp t off and t gain are calculated using the following equations: ymxb + ? = force temperature ( c) t register value y = m ? x + b m b t1 t2 t off b m ---- - = t gain m = cs5484 ds981f2 65 8. basic application circuits figure 25 shows the cs5484 configured to measure power in a single-phase, 3-wire system with two voltages and two currents. in this diagram, current transformers (cts) are used to sense the line load currents, and resistive voltage dividers are used to sense the line voltage. ct ct 5 x 250k 1k cs5484 27nf 27nf 1k 1k l1 l2 n vin2 - vin2 + iin1+ iin1- iin2+ iin2- application processor reset rx tx gnda gndd do3 do1 do2 vdda +3.3v 0.1uf 0.1uf +3 .3v vddd +3.3v vref- vref+ 0.1 uf 27nf 27nf 1k 1k ? r bu r d en wh varh 4. 096 mhz xin xout 27nf 27nf 1k ssel interrupt ? r bu r d en ? r bu r d en ? r bu r d en mode vin1 + vin1 - 27nf 27nf 1k 5 x 250k 1k zero crossings do4 +3.3v load load 0.1 uf 10 k +3 .3 v cs figure 25. typical connection (single-phase, 3-wire, 12s electricity meter) cs5484 66 ds981f2 9. package dimensions 28 qfn (5mmx5mm body with ex posed pad) package drawing mm inch dimension min nom max min nom max a 0.80 0.90 1.00 0.031 0.035 0.039 a1 0.00 0.02 0.05 0.000 0.001 0.002 a3 0.20 ref 0.008 ref b 0.20 0.25 0.30 0.008 0.010 0.012 d 5.00 bsc 0.197 bsc d2 3.50 3.65 3.80 0.138 0.144 0.150 e 0.50 bsc 0.020 bsc e 5.00 bsc 0.197 bsc e2 3.50 3.65 3.80 0.138 0.144 0.150 l 0.35 0.40 0.45 0.014 0.016 0.018 aaa 0.15 0.006 bbb 0.10 0.004 ddd 0.05 0.002 eee 0.08 0.003 notes: 1. controlling dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m. 3. this drawing conforms to jede c outline mo-220, variation vhhd-3. 4. recommended reflow profile is per jedec/ipc j-std-020. cs5484 ds981f2 67 10. ordering information 11. environmental, manufactu ring, and handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 12. revision history ordering number container temperature package CS5484-INZ bulk -40 to +85 c 28-pin qfn, lead (pb) free CS5484-INZr tape & reel part number peak reflow temp msl rating* max floor life CS5484-INZ 260c 3 7 days revision date changes pp1 apr 2012 preliminary release. f1 apr 2012 edited for content and clarity. f2 jun 2012 updated ordering information. cs5484 68 ds981f2 contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general di stribution, advertising or promotional purposes, or for creating any work for resale. certain applications usin g semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). cirrus products are not desi gned, authorized or warranted for use in products surgically implante d into the body, automoti ve safety or security devices, life support products or other crit- ical applications. incl usion of cirrus products in such ap plications is understood to be full y at the customer's risk and cir- rus disclaims and makes no warranty, express, statutory or im plied, including the implied wa rranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er's customer uses or permits the use of ci rrus products in critical ap plications, customer agrees , by such use, to fully indemnify cirrus, its officers, directors, employees, distributo rs and other agents from any and all liability, including at- torneys' fees and costs, that may result fr om or arise in connect ion with these uses. cirrus logic, cirrus, the cirrus logic logo designs, exl core, and the exl core logo design are trademarks of cirrus logic, inc . all other brand and product names in this document may be trademarks or service marks of their respective owners. spi is a trademark of motorola, inc. |
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